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82559 fast ethernet* multifunction pci/ cardbus controller networking silicon datasheet product features n optimum integration for lowest cost solution integrated ieee 802.3 10base-t and 100base-tx compatible phy glueless 32-bit pci master interface glueless cardbus master interface modem interface for combination solutions in pci, cardbus, and minipci designs pxe support in combo designs 128 kbyte flash interface integrated power management functions thin bga 15mm 2 package n wired for management and reduced total cost of ownership wired for management support system management bus support for total cost of ownership support power management capabilities acpi and pci power management standards compliance wake on interesting packets and link status change support magic packet* support remote power up support n high performance networking functions chained memory structure similar to the 82558, 82557, and 82596 improved dynamic transmit chaining with multiple priorities transmit queues backward compatible software to the 82558 and 82557 full duplex support at both 10 and 100 mbps ieee 802.3u auto-negotiation support 3 kbyte transmit and 3 kbyte receive fifos fast back-to-back transmission support with minimum interframe spacing ieee 802.3x 100base-tx flow control support adaptive technology tcp/udp checksum offload capabilities n low power features low power 3.3 v device efficient dynamic standby mode deep power down support clockrun protocol support order number: 743892-002 revision 2.0 may 1999
datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 82559 may contain design defects or errors known as errata which may cause the product to deviate from published specificat ions. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1999 * third-party brands and names are the property of their respective owners.
datasheet iii networking silicon 82559 contents 1.0 introduction................................................................................................................ ......... 1 1.1 82559 overview .................................................................................................... 1 1.2 features, enhancements, and changes to the 82559 from the 82558................. 1 1.3 enhancements to the 82559 c-step ..................................................................... 2 2.0 82559 architectural overview ............................................................................................ 3 2.1 parallel subsystem overview................................................................................ 3 2.2 fifo subsystem overview ................................................................................... 4 2.3 10/100 mbps serial csma/cd unit overview ......................................................5 2.4 10/100 mbps physical layer unit.......................................................................... 5 3.0 signal descriptions......................................................................................................... ....7 3.1 signal type definitions ......................................................................................... 7 3.2 pci bus and cardbus interface signals ............................................................... 7 3.2.1 address and data signals ....................................................................... 7 3.2.2 interface control signals ......................................................................... 8 3.2.3 system and power management signals ............................................... 9 3.3 local memory interface signals ........................................................................... 9 3.4 system management bus (smb) interface signals ........................................... 12 3.5 testability port signals ....................................................................................... 12 3.6 phy signals ....................................................................................................... 12 4.0 82559 media access control functional description....................................................... 15 4.1 82559 initialization............................................................................................... 15 4.1.1 initialization effects on 82559 units ....................................................... 15 4.1.2 initialization effects on tco functionality.............................................. 16 4.2 pci and cardbus interface ................................................................................. 16 4.2.1 82559 bus operations............................................................................ 16 4.2.2 pci mode pin ......................................................................................... 25 4.2.3 clockrun signal ...................................................................................... 25 4.2.4 power management event and card status change signals................ 26 4.3 pci power management ..................................................................................... 26 4.3.1 power states .......................................................................................... 26 4.3.2 wake-up events ..................................................................................... 31 4.4 cardbus power management ............................................................................. 32 4.5 wake on lan (preboot wake-up)....................................................................... 32 4.6 parallel flash/modem interface........................................................................... 33 4.7 serial eeprom interface.................................................................................... 33 4.8 10/100 mbps csma/cd unit............................................................................... 36 4.8.1 full duplex ............................................................................................. 37 4.8.2 flow control ........................................................................................... 37 4.8.3 address filtering modifications .............................................................. 37 4.8.4 vlan support ........................................................................................ 38 4.9 media independent interface (mii) management interface ................................. 38 5.0 82559 physical layer functional description .................................................................. 39 5.1 100base-tx phy unit ....................................................................................... 39
82559 networking silicon iv datasheet 5.1.1 100base-tx transmit clock generation .............................................. 39 5.1.2 100base-tx transmit blocks ............................................................... 39 5.1.3 100base-tx receive blocks ................................................................ 42 5.1.4 100base-tx collision detection ........................................................... 43 5.1.5 100base-tx link integrity and auto-negotiation solution.................... 43 5.1.6 auto 10/100 mbps speed selection ....................................................... 43 5.2 10base-t functionality ...................................................................................... 44 5.2.1 10base-t transmit clock generation................................................... 44 5.2.2 10base-t transmit blocks.................................................................... 44 5.2.3 10base-t receive blocks..................................................................... 44 5.2.4 10base-t collision detection................................................................ 45 5.2.5 10base-t link integrity ......................................................................... 45 5.2.6 10base-t jabber control function ....................................................... 45 5.2.7 10base-t full duplex ........................................................................... 46 5.3 auto-negotiation functionality ............................................................................ 46 5.3.1 description ............................................................................................. 46 5.3.2 parallel detect and auto-negotiation ..................................................... 46 5.4 led description .................................................................................................. 47 6.0 82559 modem functionality ............................................................................................. 49 6.1 pci address mapping to the modem .................................................................. 49 6.2 modem read and write cycles .......................................................................... 49 6.3 modem and preboot extension environment coexistence................................. 49 6.3.1 programming details.............................................................................. 49 6.3.2 support circuitry .................................................................................... 50 7.0 82559 tco functionality ................................................................................................. 51 7.1 system functionality with a tco controller ....................................................... 51 7.2 system functionality without a tco controller .................................................. 53 7.3 tco interface...................................................................................................... 53 7.3.1 smb alert signal (smbalrt#).............................................................. 53 7.3.2 alert response address (ara) cycle.................................................... 54 8.0 pci and cardbus configuration registers....................................................................... 55 8.1 function 0: lan (ethernet) pci configuration space ......................................... 55 8.1.1 pci vendor id and device id registers ................................................ 55 8.1.2 pci command register ......................................................................... 56 8.1.3 pci status register................................................................................ 57 8.1.4 pci revision id register........................................................................ 58 8.1.5 pci class code register ....................................................................... 58 8.1.6 pci cache line size register................................................................ 58 8.1.7 pci latency timer ................................................................................. 59 8.1.8 pci header type ................................................................................... 59 8.1.9 pci base address registers.................................................................. 59 8.1.10 base address registry summary .......................................................... 61 8.1.11 cardbus card information structure (cis) pointer ................................ 61 8.1.12 pci subsystem vendor id and subsystem id registers....................... 61 8.1.13 capability pointer ................................................................................... 62 8.1.14 interrupt line register............................................................................ 62 8.1.15 interrupt pin register ............................................................................. 62 8.1.16 minimum grant register ........................................................................ 62
datasheet v networking silicon 82559 8.1.17 maximum latency register.................................................................... 63 8.1.18 capability id register............................................................................. 63 8.1.19 next item pointer.................................................................................... 63 8.1.20 power management capabilities register ............................................. 63 8.1.21 power management control/status register (pmcsr)......................... 64 8.1.22 data register ......................................................................................... 64 8.2 function 1: modem pci configuration space ..................................................... 66 8.2.1 modem configuration id register .......................................................... 66 8.2.2 modem command register ................................................................... 67 8.2.3 modem status register.......................................................................... 67 8.2.4 modem revision id register.................................................................. 68 8.2.5 modem header type register ............................................................... 68 8.2.6 modem i/o base address register........................................................ 68 8.2.7 modem memory base address register................................................ 68 8.2.8 modem cardbus cis pointer .................................................................68 8.2.9 modem subsystem vendor id register ................................................. 68 8.2.10 modem subsystem id register.............................................................. 69 8.2.11 modem capabilities pointer ................................................................... 69 8.2.12 modem interrupt register....................................................................... 69 8.2.13 modem power management capabilities register ................................ 69 8.2.14 modem power management control/status register ............................ 69 8.2.15 modem data register ............................................................................ 69 8.2.16 modem support in pci mode .................................................................70 9.0 control/status registers .................................................................................................. 71 9.1 lan (ethernet) control/status registers ............................................................ 71 9.1.1 system control block status word ........................................................ 73 9.1.2 system control block command word.................................................. 73 9.1.3 system control block general pointer................................................... 74 9.1.4 port ..................................................................................................... 74 9.1.5 flash control register............................................................................ 74 9.1.6 eeprom control register..................................................................... 74 9.1.7 management data interface control register........................................ 74 9.1.8 receive direct memory access byte count........................................... 74 9.1.9 early receive interrupt........................................................................... 75 9.1.10 flow control register............................................................................. 75 9.1.11 power management driver register ...................................................... 75 9.1.12 general control register........................................................................ 76 9.1.13 general status register ......................................................................... 76 9.1.14 ethernet card status change registers ................................................ 76 9.2 statistical counters ............................................................................................. 79 9.3 modem control/status registers ........................................................................ 81 9.3.1 modem base memory addressing ......................................................... 81 9.3.2 modem base i/o addressing .................................................................82 9.3.3 modem cardbus cstchg registers ....................................................82 10.0 phy unit registers ......................................................................................................... .85 10.1 mdi registers 0 - 7 ............................................................................................. 85 10.1.1 register 0: control register bit definitions ........................................... 85 10.1.2 register 1: status register bit definitions ............................................ 86
82559 networking silicon vi datasheet 10.1.3 register 2: phy identifier register bit definitions ................................ 87 10.1.4 register 3: phy identifier register bit definitions ................................ 87 10.1.5 register 4: auto-negotiation advertisement register bit definitions .... 87 10.1.6 register 5: auto-negotiation link partner ability register bit definitions . 87 10.1.7 register 6: auto-negotiation expansion register bit definitions .......... 88 10.2 mdi registers 8 - 15 ........................................................................................... 88 10.3 mdi register 16 - 31 ........................................................................................... 88 10.3.1 register 16: phy unit status and control register bit definitions ....... 88 10.3.2 register 17: phy unit special control bit definitions ........................... 89 10.3.3 register 18: phy address register ....................................................... 90 10.3.4 register 19: 100base-tx receive false carrier counter bit definitions 90 10.3.5 register 20: 100base-tx receive disconnect counter bit definitions 90 10.3.6 register 21: 100base-tx receive error frame counter bit definitions . 90 10.3.7 register 22: receive symbol error counter bit definitions .................. 91 10.3.8 register 23: 100base-tx receive premature end of frame error counter bit definitions 91 10.3.9 register 24: 10base-t receive end of frame error counter bit definitions 91 10.3.10 register 25: 10base-t transmit jabber detect counter bit definitions .. 91 10.3.11 register 26: equalizer control and status bit definitions ...................... 91 10.3.12 register 27: phy unit special control bit definitions ........................... 92 11.0 82559 test port functionality .......................................................................................... 93 11.1 introduction ......................................................................................................... 93 11.2 asynchronous test mode ................................................................................... 93 11.3 test function description ................................................................................... 93 11.3.1 tristate ................................................................................................... 93 11.3.2 nand tree............................................................................................. 93 12.0 electrical and timing specifications................................................................................. 97 12.1 absolute maximum ratings ................................................................................ 97 12.2 dc specifications ............................................................................................... 97 12.3 ac specifications .............................................................................................. 101 12.4 timing specifications ........................................................................................ 102 12.4.1 clocks specifications ........................................................................... 102 12.4.2 timing parameters ............................................................................... 103 13.0 package and pinout information .................................................................................... 111 13.1 package information ......................................................................................... 111 13.2 pinout information ............................................................................................. 112 13.2.1 82559 pin assignments ...................................................................... 112 13.2.2 82559 ball grid array diagram ........................................................... 114 figures 1 82559 block diagram ............................................................................................ 3
datasheet vii networking silicon 82559 2 control/status register i/o read cycle.............................................................. 17 3 control/status register i/o write cycle .............................................................. 18 4 flash buffer read cycle ..................................................................................... 19 5 flash buffer write cycle...................................................................................... 20 6 pci retry cycle................................................................................................... 21 7 memory read burst cycle .................................................................................. 22 8 memory write burst cycle................................................................................... 22 9 isolate signal behavior to pci power good signal............................................. 29 10 82559 initialization upon pci rst# and isolate#........................................... 30 11 64-word eeprom read instruction waveform .................................................. 34 12 82559 eeprom format ..................................................................................... 35 13 nrz to mlt-3 encoding diagram ....................................................................... 41 14 conceptual transmit differential waveform........................................................ 41 15 auto-negotiation and parallel detect .................................................................. 47 16 two and three led schematic diagram............................................................ 48 17 modem read/write cycles.................................................................................. 49 18 support circuitry example................................................................................... 50 19 smb session....................................................................................................... 53 20 slave request for data transfer......................................................................... 54 21 pci configuration registers................................................................................ 55 22 pci command register ...................................................................................... 56 23 pci status register............................................................................................. 57 24 cache line size register.................................................................................... 58 25 base address register for memory mapping...................................................... 59 26 base address register for i/o mapping.............................................................. 60 27 modem pci configuration registers................................................................... 66 28 82559 control/status register ............................................................................ 71 29 rbias100 resistance versus transmitter current ............................................ 99 30 rbias10 resistance versus transmitter current ............................................100 31 pci/cardbus clock waveform ..........................................................................102 32 output timing measurement conditions...........................................................103 33 input timing measurement conditions..............................................................103 34 flash/modem timings for a read cycle ...........................................................106 35 flash/modem timings for a write cycle ...........................................................106 36 eeprom timings .............................................................................................107 37 10base-t nlp timings....................................................................................108 38 auto-negotiation flp timings ..........................................................................108 39 dimension diagram for the 82559 196-pin bga ...............................................111 40 82559 ball grid array diagram .........................................................................114 tables 1 eeprom words field descriptions.................................................................... 35 2 4b/5b encoder .................................................................................................... 39 3 magnetics modules ............................................................................................. 42 4 pci command register bits ............................................................................... 56 5 pci status register bits...................................................................................... 57 6 base address register functionalities................................................................ 61 7 82559 id fields programming............................................................................. 62
82559 networking silicon viii datasheet 8 power management capability register ............................................................. 63 9 power management control and status register ............................................... 64 10 82559 b-step ethernet data register ................................................................. 64 11 82559 c-step ethernet data register ................................................................. 65 12 power management control and status register ............................................... 67 13 modem status register....................................................................................... 67 14 modem revision register ................................................................................... 68 15 ethernet data register........................................................................................ 69 16 power management driver register ................................................................... 75 17 general control register .................................................................................... 76 18 general status register ...................................................................................... 76 19 lan function event register .............................................................................. 77 20 lan function event mask register .................................................................... 77 21 lan function present state register ................................................................. 78 22 lan force event register .................................................................................. 79 23 82558 statistical counters .................................................................................. 79 24 modem function event mask register ............................................................... 83 25 modem function present state register ............................................................ 83 26 nand tree chains ............................................................................................. 94 27 general dc specifications .................................................................................. 97 28 pci/cardbus interface dc specifications ........................................................... 97 29 smb interface dc specifications ........................................................................ 98 30 flash/modem/eeprom interface dc specifications ......................................... 98 31 led voltage/current characteristics .................................................................. 99 32 100base-tx voltage/current characteristics .................................................... 99 33 10base-t voltage/current characteristics ...................................................... 100 34 ac specifications for pci signaling .................................................................. 101 35 ac specifications for cardbus signaling .......................................................... 101 36 ac specifications for local bus signaling ........................................................ 101 37 pci/cardbus clock specifications .................................................................... 102 38 x1 clock specifications..................................................................................... 102 39 measure and test condition parameters ......................................................... 103 40 pci/cardbus timing parameters ...................................................................... 104 41 flash timing parameters .................................................................................. 105 42 eeprom timing parameters ........................................................................... 107 43 10base-t nlp timing parameters .................................................................. 108 44 auto-negotiation flp timing parameters ........................................................ 108 45 100base-tx transmitter ac specification........................................................ 109 46 flash timing parameters .................................................................................. 109 47 82559 pin assignments .................................................................................... 112
datasheet ix networking silicon 82559 revision history revision date revision description jan. 1999 1.0 first release. may 1999 2.0 ? preliminar y 82559 c-step updates: ? added section 1.3, "enhancements to the 82559 c-step" ? chan g ed resistance values for rbias pins in section 3.6, "phy si g - nals" ? chan g ed si g nal names ( section 3.4, "s y stem mana g ement bus ( smb ) interface si g nals" ) : ? alert bus data: alertd ( previousl y) to smbd ? alert bus clock: alertclk ( previousl y) to smbclk ? bus alert: busalrt ( previousl y) to smbalrt ? chan g ed value of pci power mana g ement in the capabilit y id re g ister from 01h to 02h ( section 8.1.18, "capabilit y id re g ister" ) ? chan g ed value of bits 18:16 in the power mana g ement capabilities re g ister from 001b to 010b ( section 8.1.20, "power mana g ement capabilities re g is- ter" ) ? chan g ed power consumption values in table 15. ethernet data re g ister in section 8.1.22, "data re g ister" ? chan g ed name of modem capabilities pointer ( modem cap_ptr ) re g ister in pci confi g uration space to modem ( section 8.2, "function 1: modem pci confi g uration space" ) ? added section 11.0, "82559 test port functionalit y "
82559 networking silicon x datasheet
networking silicon 82559 datasheet 1 1.0 introduction 1.1 82559 overview the 82559 is intel's second generation fully integrated 10base-t/100base-tx lan solution. the 82559 consists of both the media access controller (mac) and the physical layer (phy) interface combined into a single component solution. the 82559 builds on the basic functionality of the 82558. in addition to the 82558, the 82559 has added new features and enhancements: ? host-side cardbus interface ? enhanced power management implementation ? enhanced total cost of ownership (tco) support ? optimized flash or modem interface support the 32-bit pci/cardbus controller provides enhanced scatter-gather bus mastering capabilities and enables the 82559 to perform high speed data transfers over the pci bus and cardbus. its bus master capabilities enable the component to process high level commands and perform multiple operations, which lowers cpu utilization by off-loading communication tasks from the cpu. two large transmit and receive fifos of 3 kbyte each help prevent data underruns and overruns while waiting for bus accesses. this enables the 82559 to transmit data with minimum interframe spacing (ifs). the 82559 can operate in either full duplex or half duplex mode. in full duplex mode the 82559 adheres with the ieee 802.3x flow control specification. half duplex performance is enhanced by a proprietary collision reduction mechanism. the 82559 includes a simple phy interface to the wire transformer at rates of 10base-t and 100base-tx enables reduction in cost, real estate and design complexity. its auto-negotiation capability for speed, duplex, and flow control mode reduces cost, real estate, and design complexity. the 82559 also includes an interface to a serial (4-pin) eeprom and a parallel interface to a 128 kbyte flash memory. the eeprom provides power-on initialization for hardware and software configuration parameters. the parallel port can be used as either a flash memory interface or an isa-like interface for modem. combined with a total cost of ownership (tco) controller, the 82559 can help reduce the total cost of ownership in network environments. the device includes a system management bus (smb) interface enabling the tco controller to communicate with a management agent on the network. 1.2 features, enhancements, and changes to the 82559 from the 82558 ? glueless 32-bit pci bus master interface ? support for latchless flash interface with up to 128 kbyte of flash addressing ? glueless cardbus master interface
82559 networking silicon 2 datasheet ? modem interface for combination solution (lan and modem) in pci and cardbus designs ? low power consumption for lan/modem combination designs to meet cardbus power requirements ? compliance with advanced configuration and power interface and pci power management specifications ? support for wake-up on interesting packets and link status change ? support for remote power-up using wake on lan* (wol) technology ? deep power-down mode support ? support of total cost of ownership (tco) management interface and wired for management (wfm) ? backward compatible software with 82558 and 82557 ? tcp/udp checksum offload capabilities ? support for intels adaptive technology the following is a list of changes that were made from the 82558 b-step fast ethernet controller to the 82559 fast ethernet multifunction pci/cardbuscontroller. ? use of 3.3 v power supply (82559) versus 5 v power supply ? individual address, multicast address, and arp wake-up events merged into extended programmable wake-up packet command and removed from the csma command ? receive collision bit in the rfd status word replaced with a tco indication bit ? smb port implemented to support tco management interface ? phy identifier in mii register 3 modified ? external phy support removed ? phy-based flow control removed (802.3x flow control was not removed) 1.3 enhancements to the 82559 c-step the success of the 82559 b-step in mobile designs has spurred the addition of several new features to the device. these enhancements integrate new capabilities into the 82559 for both cardbus and minipci system designs: ? reducing the declared flash window requirement to 128 bytes from 1 mbyte. ? adding glueless support for pxe flash rom in lan/modem combination designs by adding an external gating signal
networking silicon 82559 datasheet 3 2.0 82559 architectural overview figure 1 is a high level block diagram of the 82559. it is divided into five main subsystems: a parallel subsystem, a fifo subsystem, the total cost of ownership (tco) subsystem, the 10/100 mbps carrier sense multiple access with collision detect (csma/cd) unit, and the 10/100 mbps physical layer (phy) unit. 2.1 parallel subsystem overview the parallel subsystem is broken down into several functional blocks: a pci bus master interface, a micromachine processing unit and its corresponding microcode rom, and a pci target control/ flash/eeprom/modem interface. the parallel subsystem also interfaces to the fifo subsystem, passing data (such as transmit, receive, and configuration data) and command and status parameters between these two blocks. the dual function lan and modem interface provides a complete glueless connection to the pci bus and is compliant with the pci bus specification, revision 2.2. the 82559 provides 32 bits of addressing and data, as well as the complete control interface to operate on a pci bus. as a pci target, it follows the pci configuration format which allows all accesses to the 82559 to be automatically mapped into free memory and i/o space upon initialization of a pci system. for processing of transmit and receive frames, the 82559 operates as a master on the pci bus, initiating zero wait state transfers for accessing these data parameters. the 82559 control/status register block is part of the pci target element. the control/status register block consists of the following 82559 internal control registers: system control block (scb), port, flash control, eeprom control, modem control and management data interface (mdi) control. the micromachine is an embedded processing unit contained in the 82559 that enables adaptive technology. the micromachine accesses the 82559 microcode rom working its way through the operation codes, opcodes (or instructions), contained in the rom to perform its functions. parameters accessed from memory such as pointers to data buffers are also used by the figure 1. 82559 block diagram 10/100 mb p s csma/cd data interface unit ( diu ) 100base-tx/ 10base-t phy four channel addressin g unit - dma pci bus interface unit ( biu ) pci tar g et and flash/modem/eeprom interface micro- machine dual ported fifo 3 kb y te rx fifo fifo control 3 kb y te tx fifo smb interface local memor y / modem interface smb interface pci/ cardbus interface tpe interface
82559 networking silicon 4 datasheet micromachine during the processing of transmit or receive frames by the 82559. a typical micromachine function is to transfer a data buffer pointer field to the 82559 dma unit for direct access to the data buffer. the micromachine is divided into two units, receive unit and command unit which includes transmit functions. these two units operate independently and concurrently. control is switched between the two units according to the microcode instruction flow. the independence of the receive and command units in the micromachine allows the 82559 to execute commands and receive incoming frames simultaneously, with no real-time cpu intervention. the 82559 contains an interface to an external flash memory, an external serial eeprom, and modem. these three interfaces are multiplexed, and both read and write accesses are supported. the flash may be used for remote boot functions, network statistical and diagnostics functions, and management functions. the flash is mapped into host system memory (anywhere within the 32-bit memory address space) for software accesses. it is also mapped into an available boot expansion rom location during boot time of the system. more information on the flash interface is detailed in section 4.6, parallel flash/modem interface on page 33 . the eeprom is used to store relevant information for a lan connection such as node address, as well as board manufacturing and configuration information. both read and write accesses to the eeprom are supported by the 82559. information on the eeprom interface is detailed in section 4.7, serial eeprom interface on page 33 . the modem interface uses an isa-like signal and is described in more detail in section 6.0, 82559 modem functionality on page 49 . 2.2 fifo subsystem overview the 82559 fifo subsystem consists of a 3 kbyte transmit fifo and 3 kbyte receive fifo. each fifo is unidirectional and independent of the other. the fifo subsystem serves as the interface between the 82559 parallel side and the serial csma/cd unit. it provides a temporary buffer storage area for frames as they are either being received or transmitted by the 82559, which improves performance: ? transmit frames can be queued within the transmit fifo, allowing back-to-back transmission within the minimum interframe spacing (ifs). ? the storage area in the fifo allows the 82559 to withstand long pci bus latencies without losing incoming data or corrupting outgoing data. ? the 82559 transmit fifo threshold allows the transmit start threshold to be tuned to eliminate underruns while concurrent transmits are being performed. ? the fifo subsection allows extended pci zero wait state burst accesses to or from the 82559 for both transmit and receive frames since the transfer is to the fifo storage area rather than directly to the serial link. ? transmissions resulting in errors (collision detection or data underrun) are retransmitted directly from the 82559 fifo, increasing performance and eliminating the need to re-access this data from the host system. ? incoming runt receive frames (in other words, frames that are less than the legal minimum frame size) can be discarded automatically by the 82559 without transferring this faulty data to the host system.
networking silicon 82559 datasheet 5 2.3 10/100 mbps serial csma/cd unit overview the csma/cd unit of the 82559 allows it to be connected to either a 10 or 100 mbps ethernet network. the csma/cd unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. the csma/cd unit can also be placed in a full duplex mode which allows simultaneous transmission and reception of frames. 2.4 10/100 mbps physical layer unit the physical layer (phy) unit of the 82559 allows connection to either a 10 or 100 mbps ethernet network. the phy unit supports auto-negotiation for 100base-tx full duplex, 100base-tx half duplex, 10base-t full duplex, and 10base-t half duplex. it also supports three led pins to indicate link status, network activity, and speed.
82559 networking silicon 6 datasheet
networking silicon 82559 datasheet 7 3.0 signal descriptions 3.1 signal type definitions 3.2 pci bus and cardbus interface signals 3.2.1 address and data signals type name description in input the input pin is a standard input only signal. out output the output pin is a totem pole output pin and is a standard active driver. t/s tri-state the tri-state pin is a bidirectional, input/output pin. s/t/s sustained tri-state the sustained tri-state pin is an active low tri-state signal owned and driven by one agent at a time. the agent asserting the s/t/ s pin low must drive it high at least one clock cycle before floating the pin. a new agent can only assert an s/t/s signal low one clock cycle after it has been tri-stated by the previous owner. o/d open drain the open drain pin allows multiple devices to share this signal as a wired-or. a/i analog input the analog input pin is used for analog input signals. a/o analog output the analog output pin is used for analog output signals. b bias the bias pin is an input bias. symbol type name and function ad[31:0] t/s address and data. the address and data lines are multiplexed on the same pci pins. a bus transaction consists of an address phase followed by one or more data phases. during the address phase, the address and data lines contain the 32-bit physical address. for i/o, this is a byte address; for configuration and memory, it is a dword address. the 82559 uses little-endian byte ordering (in other words, ad[31:24] contain the most significant byte and ad[7:0] contain the least significant byte). during the data phases, the address and data lines contain data. c/be[3:0]# t/s command and b y te enable. the bus command and byte enable signals are multiplexed on the same pci pins. during the address phase, the c/be# lines define the bus command. during the data phase, the c/be# lines are used as byte enables. the byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. pa r t / s parit y . parity is even across ad[31:0] and c/be[3:0]# lines. it is stable and valid one clock after the address phase. for data phases, par is stable and valid one clock after either irdy# is asserted on a write transaction or trdy# is asserted on a read transaction.once par is valid, it remains valid until one clock after the completion of the current data phase. the master drives par for address and write data phases; and the target, for read data phases.
82559 networking silicon 8 datasheet 3.2.2 interface control signals symbol type name and function frame# s/t/s c y cle frame. the cycle frame signal is driven by the current master to indicate the beginning and duration of a transaction. frame# is asserted to indicate the start of a transaction and de-asserted during the final data phase. irdy# s/t/s initiator read y . the initiator ready signal indicates the bus masters ability to complete the current data phase and is used in conjunction with the target ready (trdy#) signal. a data phase is completed on any clock cycle where both irdy# and trdy# are sampled asserted (low) simultaneously. trdy# s/t/s tar g et read y . the target ready signal indicates the selected devices ability to complete the current data phase and is used in conjunction with the initiator ready (irdy#) signal. a data phase is completed on any clock cycle where both irdy# and trdy# are sampled asserted (low) simultaneously. stop# s/t/s sto p . the stop signal is driven by the target to indicate to the initiator that it wishes to stop the current transaction. as a bus slave, stop# is driven by the 82559 to inform the bus master to stop the current transaction. as a bus master, stop# is received by the 82559 to stop the current transaction. idsel in initialization device select. the initialization device select signal is used by the 82559 as a chip select during pci configuration read and write transactions. this signal is provided by the host in pci systems. in a cardbus system, this pin should not be connected. devsel# s/t/s device select. the device select signal is asserted by the target once it has detected its address. as a bus master, the devsel# is an input signal to the 82559 indicating whether any device on the bus has been selected. as a bus slave, the 82559 asserts devsel# to indicate that it has decoded its address as the target of the current transaction. req# t/s re q uest. the request signal indicates to the bus arbiter that the 82559 desires use of the bus. this is a point-to-point signal and every bus master has its own req#. gnt# in grant. the grant signal is asserted by the bus arbiter and indicates to the 82559 that access to the bus has been granted. this is a point-to- point signal and every master has its own gnt#. inta# o/d interru p t a. the interrupt a signal is used to request an interrupt by the 82559. this is an active low, level triggered interrupt signal. serr# o/d s y stem error. the system error signal is used to report address parity errors. when an error is detected, serr# is driven low for a single pci clock. perr# s/t/s parit y error. the parity error signal is used to report data parity errors during all pci transactions except a special cycle. the parity error pin is asserted two clock cycles after the error was detected by the device receiving data. the minimum duration of perr# is one clock for each data phase where an error is detected. a device cannot report a parity error until it has claimed the access by asserting devsel# and completed a data phase.
networking silicon 82559 datasheet 9 3.2.3 system and power management signals 3.3 local memory interface signals symbol type name and function clk in clock. the clock signal provides the timing for all pci transactions and is an input signal to every pci device. the 82559 requires a pci clock signal (frequency greater than or equal to 16 mhz) for nominal operation. the 82559 supports clock signal suspension using the clockrun protocol. clkrun# in/out o/d clockrun. the clockrun signal is used by the system to pause or slow down the pci clock signal. it is used by the 82559 to enable or disable suspension of the pci clock signal or restart of the pci clock. when the clockrun signal is not used, this pin should be connected to an external pull-down resistor. rst# in reset. the pci reset signal is used to place pci registers, sequencers, and signals into a consistent state. when rst# is asserted, all pci output signals will be tri-stated. pme# (pci) o/d power mana g ement event. the power management event signal indicates that a power management event has occurred in a pci bus system. cstschg (cardbus)/ wol (pci) out card status chan g e/wake on lan. this pin is multiplexed to provide card status change or wake on lan signals. in a cardbus system, it is used as the card status change output signal and is an asynchronous signal to the clock signal. it indicates that a power management event has occurred in a cardbus system. in a pci system, it is used as the wol pin and provides a positive pulse of approximately 52 ms upon detection of an incoming magic packet*. isolate# in isolate. the isolate signal is used to isolate the 82559 from the pci bus. when isolate is active (low), the 82559 does not drive its pci outputs (except pme# and cstschg) or sample its pci inputs (including clk and rst#). if the 82559 is not powered by an auxiliary power source, the isolate# pin must be pulled high through a 10 k w resistor. altrst# in alternate reset. the alternate reset signal is used to reset the 82559 on power-up. in systems that support an auxiliary power supply, altrst# should be connected to a power-up detection circuit. otherwise, altrst# should be tied to v cc . vio b in volta g e in p ut/out p ut. the vio pin is the voltage bias pin and is typically connected to +5 v in a pci bus system and +3.3 v in a cardbus system. symbol type name and function fld[7:0] t/s flash/modem data in p ut/out p ut. these pins are used for flash/ modem data interface. fla[16]/ clk25 out flash address [ 16 ] /25 mhz clock. this multiplexed pin is controlled by the status of the flash address[7] (fla[7]) pin. if fla[7] is left floating, this pin is used as fla[16]; otherwise, if fla[7] is connected to a pull-up resistor, this pin is used as a 25 mhz clock. fla[15]/ eesk out flash address [ 15 ] /eeprom data out p ut. during flash accesses, this multiplexed pin acts as the flash address [15] output signal. during eeprom accesses, it acts as the serial shift clock output to the eeprom.
82559 networking silicon 10 datasheet fla[14]/ eedo in/out flash address [ 14 ] /eeprom data out p ut. during flash accesses, this multiplexed pin acts as the flash address [14] output signal. during eeprom accesses, it acts as serial input data to the eeprom data output signal. fla[13]/ eedi out flash address [ 13 ] /eeprom data in p ut. during flash accesses, this multiplexed pin acts as the flash address [13] output signal. during eeprom accesses, it acts as serial output data to the eeprom data input signal. fla[12]/ mcntsm# out o/d flash address [ 12 ] /modem central site mode. this multiplexed pin acts as the flash address[12] output signal in a non-modem card. if modem is enabled, it is used as an output signal to the modem. it is either floated by default or driven low by the modem system control registers. fla[11]/ mint in/out flash address [ 11 ] /modem interru p t. this multiplexed pin acts as the flash address[11] output signal in a non-modem card. if modem is enabled, it is used as the modem interrupt input signal. fla[10]/ mring# in/out flash address [ 10 ] /modem rin g . this multiplexed pin acts as the flash address[10] output signal in a non-modem card. if modem is enabled, it is used as the modem ring input signal. fla[9]/ mrst out flash address [ 9 ] /modem reset. this multiplexed pin acts as the flash address[9] output signal in a non-modem card. if modem is enabled, it acts as the modem reset signal with an active high output. fla[8]/ iochrdy in/out flash address [ 8 ] /isa in p ut/out p ut channel read y . this multiplexed pin acts as the flash address[8] output signal in a non- modem card. if modem is enabled, it is used as the isa iochrdy input signal. fla[7]/ clken t/s flash address [ 7 ] /clock enable. this is a multiplexed pin and acts as the flash address[7] output signal during nominal operation. when the pci rst# signal is active, this pin acts as input control over the fla[16]/clk25 output signal. if the fla[7]/clken pin is connected to a pull-up resistor (3.3 k w ), a 25 mhz clock signal is provided on the fla[16]/clk25 output; otherwise, it is used as fla[16] output. fla[6:2] out flash address [ 6:2 ] . these pins are used as flash address outputs to support 128 kbyte flash addressing. if the modem is enabled, these pins carry modem address bits 6:2. fla[1]/ auxpwr t/s flash address [ 1 ] /auxiliar y power. this multiplexed pin acts as the flash address[1] output signal during nominal operation. if the modem is enabled, this pin carries modem address bit 1. when rst is active (low), it acts as the power supply indicator. if the 82559 is fed pci power, this pin should be connected to a pull-down resistor; if the 82559 is fed by auxiliary power, this pin should be connected to a pull- up resistor. fla[0]/ pcimode# t/s flash address [ 0 ] /pci mode. this multiplexed pin acts as the flash address[0] output signal during nominal operation. if the modem is enabled, this pin carries modem address bit 0. when rst# is active (low), it acts as the input system type. if the 82559 is used in a cardbus system, this pin should be connected to a pull-up resistor (3.3 k w ); otherwise, the 82559 considers the host as a pci system. eecs out eeprom chi p select. the eeprom chip select signal is used to assert chip select to the serial eeprom. flcs#/aen out flash chi p select/address enable. the flash chip select signal is active during flash. in modem mode, it acts as an isa-like address enable signal (modem chip select). symbol type name and function
networking silicon 82559 datasheet 11 floe# out flash out p ut enable. this pin provides an active low output enable control (read) to the flash memory. if the modem is enabled, this is an active-low output enable (read) of the modem. flwe# out flash write enable. this pin provides an active low write enable control to the flash memory. if the modem is enabled, this is an active low write-enable to the modem. cfcs# out securit y asic chi p select. this pin provides an active low function enable to enable/disable flash memory in combo designs. this signal is asserted high to enable flash memory in lan/modem designs. if this signal is asserted low, the modem device is enabled, and local bus signals are defined for modem. this pin is controlled by setting/ clearing the boot enable bit in the bootrom bar. this bit is set following a pci reset enabling external flash. cfclk out securit y asic clock. this pin provides a clock out to a companion asic residing on the local bus. this pin should be left unconnected in designs that do not utilize a companion asic on the flash interface. symbol type name and function
82559 networking silicon 12 datasheet 3.4 system management bus (smb) interface signals 3.5 testability port signals 3.6 phy signals symbol type name and function smbd in o/d alert bus data. this signal is stable when the alert bus clock signal is high. this open drain signal should be pulled high to v cc in all cases. smbclk in o/d alert bus clock. this pin is used for the alert bus clock signal. one clock pulse is generated for each data bit transferred. it is an open drain signal and should be pulled high to v cc in all cases. smbalrt# o/d bus alert. the bus alert pin is used as an interrupt si g nal for a slave device on the alert bus. it is an open drain si g nal and should be pulled hi g h to v cc in all cases. symbol type name and function test in test port. if this input pin is high, the 82559 will enable the test port. during nominal operation this pin should be connected to a pull-down resistor. tck in test port clock. this pin is used for the test port clock signal. ti in test port data in p ut. this pin is used for the test port data input signal. texec in test port execute enable. this pin is used for the test port execute enable signal. to out test port data out p ut. this pin is used for the test port data output signal. symbol type name and function x1 a/i cr y stal in p ut one. x1 and x2 can be driven by an external 3.3 v 25 mhz crystal. otherwise, x1 may be driven by an external metal-oxide semiconductor (mos) level 25 mhz oscillator when x2 is left floating. x2 a/o cr y stal in p ut two. x1 and x2 can be driven by an external 3.3 v 25 mhz crystal. otherwise, x1 may be driven by an external mos level 25 mhz oscillator when x2 is left floating. tdp tdn a/o analo g twisted pair ethernet transmit differential pair. these pins transmit the serial bit stream for transmission on the unshielded twisted pair (utp) cable. the current-driven differential driver can be two-level (10base-t) or three-level (100base-tx) signals depending on the mode of operation. these signals interface directly with an isolation transformer. rdp rdn a/i analo g twisted pair ethernet receive differential pair. these pins receive the serial bit stream from the isolation transformer. the bit stream can be two-level (10base-t) or three-level (100base-tx) signals depending on the mode of operation.
networking silicon 82559 datasheet 13 actled# out activit y led. the activity led pin indicates either transmit or receive activity. when activity is present, the activity led is on; when no activity is present, the activity led is off. in wake on lan mode, the actled# signal is used to indicate that the received frame passed mac address filtering. liled# out link inte g rit y led. the link integrity led pin indicates link integrity. if the link is valid in either 10 or 100 mbps, the led is on; if link is invalid, the led is off. speedled# out s p eed led. the speed led pin indicates the speed. the speed led will be on at 100 mbps and off at 10 mbps. rbias100 b reference bias resistor ( 100 mb p s ) . this pin should be connected to a 619 w pull-down resistor. a rbias10 b reference bias resistor ( 10 mb p s ) . this pin should be connected to a 549 w pull-down resistor. b vref b volta g e reference. this pin is connected to a 1.25 v 1% external voltage reference generator. to use the internal voltage reference source, this pin should be left floating. under normal circumstances, the internal voltage reference should be used and this pin would be left open. a. 619 w for rbias 100 is only a recommended value and should be fine tuned for various designs. b. 549 w for rbias 10 is only a recommended value and should be fine tuned for various designs. symbol type name and function
82559 networking silicon 14 datasheet
networking silicon 82559 datasheet 15 4.0 82559 media access control functional description 4.1 82559 initialization the 82559 has four sources for initialization. they are listed according to their precedence: 1. altrst# signal 2. pci rst# signal 3. software reset (software command) 4. selective reset (software command) 4.1.1 initialization effects on 82559 units the following table shows the effect of each of the different initialization sources on major portions of the 82559. the initialization sources are listed in order of precedence. for example, any resource that is initialized by the software reset is also initialized by the d3 to d0 transition and altrst# and pci rst# but not necessarily by the selective reset. altrst# pci rst# isolate# d3 to d0 transition software reset selective reset eeprom read and initialization xxx -- -- -- loadable microcode decoded/reset xx -- xx -- mac configuration reset and multicast hash xxxxx -- memory pointers and mircomachine state reset xx -- xxx pci configuration register reset xxxx -- -- phy configuration reset xx -- -- -- -- power management event reset x clear only if no auxiliary power present -- -- -- -- statistic counters reset xx -- xx --
82559 networking silicon 16 datasheet 4.1.2 initialization effects on tco functionality the 82559 has the ability to be controlled by two masters, the host cpu on the pci bus and the tco controller on the smb. the 82559 may be initialized by the pci bus during smb operation. the table below summarizes the effect of those sources: 4.2 pci and cardbus interface 4.2.1 82559 bus operations after configuration, the 82559 is ready for its normal operation. as a fast ethernet controller, the role of the 82559 is to access transmitted data or deposit received data. in both cases the 82559, as a bus master device, will initiate memory cycles via the pci bus to fetch or deposit the required data. in order to perform these actions, the 82559 is controlled and examined by the cpu via its control and status structures and registers. some of these control and status structures reside in the 82559 and some reside in system memory. for access to the 82559s control/status registers (csr), the 82559 acts as a slave (in other words, a target device). the 82559 serves as a slave also while the cpu accesses its 128 kbyte flash buffer or its eeprom. when the 82559 is in modem mode, it also acts as a slave. details regarding modem interface are described in section 4.6, parallel flash/ modem interface on page 33 . section 4.2.1.1, 82559 bus slave operation describes the 82559 slave operation. it is followed by a description of the 82559 operation as a bus master (initiator) in section 4.2.1.2, 82559 bus master operation on page 22 . 4.2.1.1 82559 bus slave operation the 82559 serves as a target device in one of the following cases: ? cpu accesses to the 82559 system control block (scb) control/status registers (csr) initialization source smb behavior status and receive enable altrst#, pci rst#, or isolate# a the smb is terminated instantaneously. b initialized to inactive d3 to d0 transition the smb cycle is aborted. during smb read commands, the 82559 transfers zeros until the end of the cycle. an smb write cycle has no effect on the 82559. the 82559 asserts the smbalrt# after a d3 to d0 transition. the 82559 indicates its initialization status to the tco controller via an active initialization bit in the status word. initialized to inactive software reset, selective reset, or d3 to d0 transition the smb cycle is aborted. during smb read commands, the 82559 transfers zeros until the end of the cycle. an smb write cycle has no affect on the 82559. after a software reset, the 82559 reports its initialization in the same manner as in a d3 to d0 transition. unaffected a. isolate# acts as reset on its trailing edge. while the 82559 is in the d3 power state, the pci rst# initializes the 82559 on the trailing edge. b. smb commands in process will be terminated immediately.
networking silicon 82559 datasheet 17 ? cpu accesses to the eeprom through its csr ? cpu accesses to the 82559 port address via the csr ? cpu accesses to the mdi control register in the csr ? cpu accesses to the flash control register in the csr ? cpu accesses to the 128 kbyte flash the csr and the 1 mbyte flash buffer are considered by the 82559 as two totally separated memory spaces. the 82559 provides separate base address registers (bars) in the configuration space to distinguish between them. the size of the csr memory space is 4 kbyte in the memory space and 64 bytes in the i/o space. the 82559 treats accesses to these memory spaces differently. 4.2.1.1.1 control/status register (csr) accesses the 82559 supports zero wait state single cycle memory or i/o mapped accesses to its csr space. separate bars request 4 kbytes of memory space and 64 bytes of i/o space to accomplish this. based on its needs, the software driver will use either memory or i/o mapping to access these registers. the 82559 provides 4 valid kbytes of csr space, which include the following elements: ? system control block (scb) registers ? port register ? flash control register ? eeprom control register ? mdi control register ? flow control registers ? cardbus registers the figures below show csr zero wait state i/o read and write cycles. in the case of accessing the control/status registers, the cpu is the initiator and the 82559 is the target of the transaction. figure 2. control/status register i/o read cycle system 82559 clk frame# c/be# irdy# trdy# devsel# ad 34 2 1 56789 addr data i/o rd be# stop#
82559 networking silicon 18 datasheet read accesses: the cpu, as the initiator, drives address lines ad[31:0], the command and byte enable lines c/be#[3:0] and the control lines irdy# and frame#. as a slave, the 82559 controls the trdy# signal and provides valid data on each data access. the 82559 allows the cpu to issue only one read cycle when it accesses the control/status registers, generating a disconnect by asserting the stop# signal. the cpu can insert wait states by de-asserting irdy# when it is not ready. write accesses: the cpu, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be#[3:0] and the control lines irdy# and frame#. it also provides the 82559 with valid data on each data access immediately after asserting irdy#. the 82559 controls the trdy# signal and asserts it from the data access. the 82559 allows the cpu to issue only one i/o write cycle to the control/status registers, generating a disconnect by asserting the stop# signal. this is true for both memory mapped and i/o mapped accesses. figure 3. control/status register i/o write cycle system 82559 clk frame# c/be# irdy# trdy# devsel# ad 34 2 1 56789 addr data i/o wr be# stop#
networking silicon 82559 datasheet 19 4.2.1.1.2 flash buffer accesses the cpu accesses to the flash buffer are very slow. for this reason the 82559 issues a target- disconnect at the first data access. the 82559 asserts the stop# signal to indicate a target- disconnect. the figures below illustrate memory cpu read and write accesses to the 128 kbyte flash buffer. the longest burst cycle to the flash buffer contains one data access only. read accesses: the cpu, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be#[3:0] and the control lines irdy# and frame#. the 82559 controls the trdy# signal and de-asserts it for a certain number of clocks until valid data can be read from the figure 4. flash buffer read cycle system 82559 clk frame# c/be# irdy# trdy# devsel# ad addr data mem rd be# stop#
82559 networking silicon 20 datasheet flash buffer. when trdy# is asserted, the 82559 drives valid data on the ad[31:0] lines. the cpu can also insert wait states by de-asserting irdy# until it is ready. flash buffer read accesses can be byte or word length. write accesses: the cpu, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be#[3:0] and the control lines irdy# and frame# . it also provides the 82559 with valid data immediately after asserting irdy# . the 82559 controls the trdy# signal and de- asserts it for a certain number of clocks until valid data is written to the flash buffer. by asserting trdy# , the 82559 signals the cpu that the current data access has completed. flash buffer write accesses can be byte length only. 4.2.1.1.3 retry premature accesses the 82559 responds with a retry to any configuration cycle accessing the 82559 before the completion of the automatic read of the eeprom. the 82559 may continue to retry any configuration accesses until the eeprom read is complete. the 82559 does not enforce the rule that the retried master must attempt to access the same address again in order to complete any delayed transaction. any master access to the 82559 after the completion of the eeprom read will be honored. figure 6 below depicts how a retry looks when it occurs. figure 5. flash buffer write cycle system 82559 clk frame# c/be# irdy# trdy# devsel# ad addr mem wr be# stop# data
networking silicon 82559 datasheet 21 note: the 82559 is considered the target in the above diagram; thus, trdy# is not asserted. a retry may also occur in the following two scenarios: ? card information structure (cis) in memory is accessed in cardbus mode. ? external modem registers are accessed and the modem does not assert iochrdy within 7 pci clocks from the assertion of mdmcs#. 4.2.1.1.4 error handling data parity errors: the 82559 checks for data parity errors while it is the target of the transaction. if an error was detected, the 82559 always sets the detected parity error bit in the pci configuration status register, bit 15. the 82559 also asserts perr#, if the parity error response bit is set (pci configuration command register, bit 6). the 82559 does not attempt to terminate a cycle in which a parity error was detected. this gives the initiator the option of recovery. target-disconnect: the 82559 prematurely terminate a cycle in the following cases: ? after accesses to the flash buffer ? after accesses to its csr ? after accesses to the configuration space system error: the 82559 reports parity error during the address phase using the serr# pin. if the serr# enable bit in the pci configuration command register or the parity error response bit are not set, the 82559 only sets the detected parity error bit (pci configuration status register, bit 15). if serr# enable and parity error response bits are both set, the 82559 sets the signaled system error bit (pci configuration status register, bit 14) as well as the detected parity error bit and asserts serr# for one clock. the 82559, when detecting system error, will claim the cycle if it was the target of the transaction and continue the transaction as if the address was correct. note: the 82559 will report a system error for any parity error during an address phase, whether or not it is involved in the current transaction. figure 6. pci retry cycle system 82559 clk frame# irdy# trdy# devsel# stop#
82559 networking silicon 22 datasheet 4.2.1.2 82559 bus master operation as a pci bus master, the 82559 initiates memory cycles to fetch data for transmission or deposit received data and for accessing the memory resident control structures. the 82559 performs zero wait state burst read and write cycles to the host main memory. figure 7 and figure 8 depict memory read and write burst cycles. for bus master cycles, the 82559 is the initiator and the host main memory (or the pci host bridge, depending on the configuration of the system) is the target. the cpu provides the 82559 with action commands and pointers to the data buffers that reside in host main memory. the 82559 independently manages these structures and initiates burst memory cycles to transfer data to and from them. the 82559 uses the memory read multiple (mr multiple) command for burst accesses to data buffers and the memory read line (mr line) command for burst accesses to control structures. for all write accesses to the control structure, the 82559 uses the memory write (mw) command. for write accesses to data structure, the 82559 may use either the memory write or memory write and invalidate (mwi) commands. figure 7. memory read burst cycle 82559 system clk frame# c/be# irdy# trdy# devsel# ad 34 2 1 5678910 addr data mr be# be# data data data data figure 8. memory write burst cycle 82559 system clk frame# c/be# irdy# trdy# devsel# ad 34 2 1 5678910 addr data mw be# be# data data data data
networking silicon 82559 datasheet 23 read accesses: the 82559 performs block transfers from host system memory in order to perform frame transmission on the serial link. in this case, the 82559 initiates zero wait state memory read burst cycles for these accesses. the length of a burst is bounded by the system and the 82559s internal fifo. the length of a read burst may also be bounded by the value of the transmit dma maximum byte count in the configure command. the transmit dma maximum byte count value indicates the maximum number of transmit dma pci cycles that will be completed after an 82559 internal arbitration. (details on the configure command are described in the 10/100 mbit family software developers manual .) the 82559, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be#[3:0] and the control lines irdy# and frame#. the 82559 asserts irdy# to support zero wait state burst cycles. the target signals the 82559 that valid data is ready to be read by asserting the trdy# signal. write accesses: the 82559 performs block transfers to host system memory during frame reception. in this case, the 82559 initiates memory write burst cycles to deposit the data, usually without wait states. the length of a burst is bounded by the system and the 82559s internal fifo threshold. the length of a write burst may also be bounded by the value of the receive dma maximum byte count in the configure command. the receive dma maximum byte count value indicates the maximum number of receive dma pci transfers that will be completed before the 82559 internal arbitration. (details on the configure command are described in the 10/100mbit family software developers manual .) the 82559, as the initiator, drives the address lines ad[31:0], the command and byte enable lines c/be#[3:0] and the control lines irdy# and frame#. the 82559 asserts irdy# to support zero wait state burst cycles. the 82559 also drives valid data on ad[31:0] lines during each data phase (from the first clock and on). the target controls the length and signals completion of a data phase by de-assertion and assertion of trdy#. cycle completion: the 82559 completes (terminates) its initiated memory burst cycles in the following cases: ? normal completion : all transaction data has been transferred to or from the target device (for example, host main memory). ? backoff : latency timer has expired and the bus grant signal (gnt#) was removed from the 82559 by the arbiter, indicating that the 82559 has been preempted by another bus master. ? transmit or receive dma maximum byte count : the 82559 burst has reached the length specified in the transmit or receive dma maximum byte count field in the configure command block. (details relating to this field and the configure command are described in the 10/100 mbit family software developers manual .) ? target termination : the target may request to terminate the transaction with a target- disconnect, target-retry, or target-abort. in the first two cases, the 82559 initiates the cycle again. in the case of a target-abort, the 82559 sets the received target-abort bit in the pci configuration status field (pci configuration status register, bit 12) and does not re-initiate the cycle. ? master abort : the target of the transaction has not responded to the address initiated by the 82559 (in other words, devsel# has not been asserted). the 82559 simply de-asserts frame# and irdy# as in the case of normal completion. ? error condition : in the event of parity or any other system error detection, the 82559 completes its current initiated transaction. any further action taken by the 82559 depends on the type of error and other conditions.
82559 networking silicon 24 datasheet 4.2.1.2.1 memory write and invalidate the 82559 has four direct memory access (dma) channels. of these four channels, the receive dma is used to deposit the large number of data bytes received from the link into system memory. the receive dma uses both the memory write (mw) and the memory write and invalidate (mwi) commands. in order to use mwi, the 82559 must guarantee the following: 1. minimum transfer of one cache line 2. active byte enable bits (or be#[3:0] are all low) during mwi access 3. the 82559 may cross the cache line boundary only if it intends to transfer the next cache line too. in order to ensure the above conditions, the 82559 may use the mwi command only if the following conditions hold: 1. the cache line size (cls) written in the cls register during pci configuration is 8 or 16 dwords. 2. the accessed address is cache line aligned. 3. the 82559 has at least 8 or 16 dwords of data in its receive fifo. 4. there are at least 8 or 16 dwords of data space left in the system memory buffer. 5. the mwi enable bit in the pci configuration command register, bit 4, should is set to 1b. 6. the mwi enable bit in the 82559 configure command should is set to 1b. (details on the configure command are described in the 10/100 mbit family software developers manual .) if any one of the above conditions does not hold, the 82559 will use the mw command. if a mwi cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than cls), then the 82559 terminates the mwi cycle at the end of the cache line. the next cycle will be either a mw or mwi cycle depending on the conditions listed above. if the 82559 started a mw cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the terminate write on cache line configuration bit of the 82559 configure command (byte 3, bit 3). if this bit is set, the 82559 terminates the mw cycle and attempts to start a new cycle. the new cycle is a mwi cycle if this bit is set and all of the above listed conditions are met. if the bit is not set, the 82559 continues the mw cycle across the cache line boundary if required. (details on the configure command are described in the 10/100 mbit family software developers manual .) 4.2.1.2.2 read align the read align feature enhances the 82559s performance in cache line oriented systems. in these particular systems, starting a pci transaction on a non-cache line aligned address may cause low performance. in order to resolve this performance anomaly, the 82559 attempts to terminate transmit dma cycles on a cache line boundary and start the next transaction on a cache line aligned address. this feature is enabled when the read align enable bit is set in the 82559 configure command (byte 3, bit 2). (details on the configure command are described in the 10/100 mbit family software developers manual .) if this bit is set, the 82559 operates as follows:
networking silicon 82559 datasheet 25 ? when the 82559 is almost out of resources on the transmit dma (that is, the transmit fifo is almost full), it attempts to terminate the read transaction on the nearest cache line boundary when possible. ? when the arbitration counters feature is enabled (in other words, the transmit dma maximum byte count value is set in the configure command), the 82559 switches to other pending dmas on cache line boundary only. note the following: ? this feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. ? this feature should be used only when the cls register in pci configuration space is set to 8 or 16. ? the 82559 reads all control data structures (including receive buffer descriptors) from the first dword (even if it is not required) in order to maintain cache line alignment. 4.2.1.2.3 error handling data parity errors: as an initiator, the 82559 checks and detects data parity errors that occur during a transaction. if the parity error response bit is set (pci configuration command register, bit 6), the 82559 also asserts perr# and sets the data parity detected bit (pci configuration status register, bit 8). in addition, if the error was detected by the 82559 during read cycles, it sets the detected parity error bit (pci configuration status register, bit 15). 4.2.2 pci mode pin during pci reset the 82559 samples the pcimode# (multiplexed with fla0) input signal to determine the nature of the host system. if the pcimode# signal is sampled low when rst# is active, the host system bus is a pci system. if pcimode# is sampled high during reset, the host system is a cardbus system. in a cardbus system, the pcimode# pin should be connected to a pull-up resistor; otherwise, the 82559 assumes it is a pci system. 4.2.3 clockrun signal the clkrun# signal is used to control the pci clock as defined in the cardbus specification and pci mobile design guide and is compliant with both the cardbus specification and pci mobile design guide. this signal is active in both the cardbus and pci bus operating modes. the clockrun signal is an open drain i/o signal. it is used as a bidirectional channel between the host and the devices. ? the host de-asserts the clkrun# signal to indicate that the clock is about to be stopped or slowed down to a non-operational frequency. ? the host asserts the clkrun# signal when the interface clock is either running at a normal operating frequency or about to be started. ? the 82559 asserts the clkrun# signal to indicate that it needs the pci clock to prevent the host from stopping the pci clock or to request that the host restore the clock if it was previously stopped. proper operation requires that the system latency from the nominal pci clk to clkrun# assertion should be less than 0.5 m s. if the system latency is longer than 0.5 m s, the occurrence of receive overruns increases. for use in these types of systems, the clockrun functionality should be
82559 networking silicon 26 datasheet disabled ( section 9.1.12, general control register on page 76 ). in this case, the 82559 will claim the pci clock even during idle time. if the clkrun# signal is not used, it should be connected to a pull-down resistor. 4.2.4 power management event and card status change signals the 82559 supports power management indications in both the pci and cardbus mode. in cardbus systems, the cstschg pin is used for power management event indication. the pme# output pin provides an indication of a power management event in pci systems. the cstschg pin is supported by four registers located in the control/status register ( section 9.0, control/ status registers on page 71 describes these registers in more detail): ? event register ? mask register ? present state register ? force event register 4.3 pci power management in addition to the base functionality of the 82558 b-step, the 82559 supports a larger set of wake-up packets and the capability to wake the system on a link status change from a low power state. these added power management enhancements enable the 82559 to adhere to emerging standards. the 82559 enables the host system to be in a sleep state and remain virtually connected to the network. after a power management event or link status change is detected, the 82559 will wake the host system. the sections below describe these events, the 82559 power states, and estimated power consumption at each power state. 4.3.1 power states the 82559 contains two sets of power management registers, one for pci and one for cardbus, and implements all four power states as defined in the power management network device class reference specification, revision 1.0. the four states, d0 through d3, vary from maximum power consumption at d0 to the minimum power consumption at d3. pci transactions are only allowed in the d0 state, except for host accesses to the 82559s pci configuration registers. the d1 and d2 power management states enable intermediate power savings while providing the system wake-up capabilities. in the d3 cold state, the 82559 can provide wake-up capabilities only if auxiliary power is supplied. wake-up indications from the 82559 are provided by the power management event (pme#) signal in pci implementations and the card status change (cstschg) signal in cardbus designs. in addition to providing a host interface through the pci bus, the 82559 provides tco controller access through a dedicated system management bus (smb). additional information on the supported tco functionality at all power states is described in section 7.0, 82559 tco functionality on page 51 .
networking silicon 82559 datasheet 27 4.3.1.1 d0 power state as defined in the network device class reference specification, the device is fully functional in the d0 power state. in this state, the 82559 receives full power and should be providing full functionality. in the 82559 the d0 state is partitioned into two substates, d0 uninitialized (d0u) and d0 active (d0a). d0u is the 82559s initial power state following a power on reset event and prior to the base address registers (bars) being accessed. while in the d0u state, the 82559 has pci slave functionality to support its initialization by the host and supports wake on lan* mode. initialization of the csr, memory, or i/o base address registers in the pci configuration space switches the 82559 from the d0u state to the d0a state. in the d0a state, the 82559 provides its full functionality and consumes its nominal power. in addition, the 82559 supports wake on link status change (see section 4.3.2, wake-up events on page 31 ). while it is active, the 82559 requires a nominal pci clock signal (in other words, a clock frequency greater than 16 mhz) for proper operation. during idle time, the 82559 supports a pci clock signal suspension using the clockrun signal mechanism. the 82559 supports a dynamic standby mode. in this mode, the 82559 is able to save almost as much power as it does in the static power-down states. the transition to or from standby is done dynamically by the 82559 and is transparent to the software. 4.3.1.2 d1 power state in order for a device to meet the d1 power state requirements, as specified in the advanced configuration and power interface (acpi) specification, revision 1.0, it must not allow bus transmission or interrupts; however, bus reception is allowed. therefore, device context may be lost and the 82559 does not initiate any pci activity. in this state, the 82559 responds only to pci accesses to its configuration space and system wake-up events. the 82559 retains link integrity and monitors the link for any wake-up events such as wake-up packets or link status change. following a wake-up event, the 82559 asserts the pme# signal to alert the pci based system or the cstschg signal for a cardbus system. 4.3.1.3 d2 power state the acpi d2 power state is similar in functionality to the d1 power state. if the bus is in the b2 state, the 82559 will consume less current than it does in the d1 state. in addition to d1 functionality, the 82559 can provide a lower power mode with wake-on-link status change capability. the 82559 may enter this mode if the link is down while the 82559 is in the d2 state. in this state, the 82559 monitors the link for a transition from an invalid link to a valid link. the 82559 will not attempt to keep the link alive by transmitting idle symbols or link integrity pulses. 1 the sub-10 ma state due to an invalid link can be enabled or disabled by a configuration bit in the power management driver register (pmdr). 4.3.1.4 d3 power state in the d3 power state, the 82559 has the same capabilities and consumes the same amount of power as it does in the d2 state. however, it enables the pci system to be in the b3 state. if the pci system is in the b3 state (in other words, no pci power is present), the 82559 provides wake-up 1. for a topology of two 82559 devices connected by a crossed twisted-pair ethernet cable, the deep power-down mode should be di sabled. if it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes become active.
82559 networking silicon 28 datasheet capabilities if it is connected to an auxiliary power source in the system. if pme is disabled, the 82559 does not provide wake-up capability or maintain link integrity. in this mode the 82559 consumes its minimal power. the 82559 enables a system to be in a sub-5 watt state (low power state) and still be virtually connected. more specifically, the 82559 supports full wake-up capabilities while it is in the d3 cold state. the 82559 can be connected to an auxiliary power source (v aux ), which enables it to provide wake-up functionality while the pci power is off. the typical current consumption of the 82559 is 125 ma at 3.3 v. thus, a dual power plane is not required. if connected to an auxiliary power source, the 82559 receives all of its power from the auxiliary source in all power states. when connected to an auxiliary power supply, the 82559 is required to have a status indicator of whether or not the power supply is valid (in other words, auxiliary power is stable). the indication is received at the auxpwr pin, as described next. 4.3.1.4.1 auxiliary power signal the 82559 senses whether it is connected to the pci power supply or to an auxiliary power supply (v aux ) via the fla1/auxpwr pin. the auxiliary power detection pin (multiplexed with fla1) is sampled when the pci rst# or altrst# signals are active. an external pull-up resistor should be connected to the 82559 if it is fed by v aux ; otherwise, the fla1/auxpwr pin should be left floating. the presence of auxpwr affects the value reported in the power management capability register (pci configuration space, offset deh). the power management capability register is described in more detail in section 8.1.20, power management capabilities register on page 63 . 4.3.1.4.2 alternate reset signal the 82559s altrst# input pin functions as a power-on reset input. following altrst# being driven low, the 82559 is initialized to a known state. in systems that support auxiliary power, this pin should be connected to the auxiliary powers power stable signal (power good) of the 82559s power source. in a lan on motherboard (lom) solution, this signal is available on the system. in network adapter implementations, an external analog device connected to the auxiliary power supply can be used to produce this signal. in systems that do not have an auxiliary power source, the altrst# signal should be tied to a pull-up resistor. 4.3.1.4.3 isolate signal when the 82559 is connected to v aux , it may be powered on while the pci bus is powered off. in this case, the 82559 isolates itself from the pci bus. the 82559 has a dedicated isolate# pin that should be connected to the pci power sources stable power signal (power good). whenever the pci bus is in the b3 state, the pci power good signal becomes inactive and the 82559 isolates itself from the pci bus. during this state, the 82559 ignores all pci signals including the rst# and clk signals. it also tristates all pci outputs, except the pme# signal. in the transition to an active pci power state (in other words, from b3 power state to b0 power state), the pci power good signal shifts high.
networking silicon 82559 datasheet 29 in a lan on motherboard solution, the pci power good signal is supplied by the system. in network adapter implementations, the pci power good signal can be generated locally using an external analog device. in these designs, the isolate# signal should envelope the systems pci power good signal as shown in figure 9 . in many systems, the pci rst# signal is asserted low whenever the pci bus is inactive. in these systems, the 82559 b-step device and later devices allow the isolate# pin to be driven from the pci rst# signal. in this case, the altrst# pin on the 82559 should be pulled high to the pci bus high voltage level. 4.3.1.4.4 pci reset signal the pci rst# signal may be activated in one of the following cases: ? power-up ? warm boot ? wake-up (b3 to b0 transition) ? set to power-down (b0 to b3 transition) if pme is enabled (in the pci power management registers), the rst# signal does not affect any pme related circuits (in other words, the cstschg registers (cardbus only), pci power management registers, and the wake-up packet would not be affected). while the rst# signal is active, the 82559 ignores other pci signals and floats its outputs. however, if auxpwr is asserted, the rst# signal has no affect on any circuitry. while the 82559 is in the d0, d1, or d2 power state, it is initialized by the rst# level. when the 82559 is in the d3 power state, the system bus may be in the b3 bus power state. in the b3 power state, the pci rst# signal is undefined; however, the auxiliary power source proposal for the pci specification, revision 2.2 is for the pci rst# signal to be an active low. therefore, the 82559 uses the pci rst# similarly to the isolate# signal in d3 power state. following the trailing edge of the pci rst#, the 82559 is initialized while preserving the pme# signal and its context. note: according to the pci specification, during the b3 state, the rst# signal is undefined. the transition from the b3 power state to the b0 power state occurs on the trailing edge of the rst# signal. the initialization signal is generated internally in the following cases: ? active rst# signal while the 82559 is the d0, d1, or d2 power state ? rst# trailing edge while the 82559 is in the d3 power state ? isolate# trailing edge figure 9. isolate signal behavior to pci power good signal pci power good signal required isolate# signal behavior
82559 networking silicon 30 datasheet the internal initialization signal resets the pci configuration space, mac configuration, and memory structure. the behavior of the pci rst# signal and the internal 82559 initialization signal are shown in the figure below. the tables below summarizes the 82559s functionality and power consumption at the different power states. note: all values shown for the d3 state assume the availability of 3.3 v standby available to the device. figure 10. 82559 initialization upon pci rst# and isolate# pci rst# internal hardware reset pci rst# internal hardware reset isolate# internal hardware reset d0 - d2 power state d3 power state internal reset due to isolate# 640 ns 640 ns power state conditions 100 mbs 10 mbs d0 maximum 175 ma 140 ma d0 average (5 mbps) 125 ma 115 ma d0 dynamic standby (with network load) 120 ma 55 ma d0u cardbus with pci clk < 70 ma < 70 ma d2/d3 (link down) pci clk 10 ma 10 ma without pci clk 3 ma 3 ma dx (x>0 with pme# disabled) pci clk 10 ma 10 ma without pci clk 3 ma 3 ma wol wake on lan power down < 3 ma < 3 ma
networking silicon 82559 datasheet 31 . 4.3.2 wake-up events there are two types of wake-up events: interesting packets and link status change. these two events are detailed below. note: the wake-up event is supported only if the pme enable bit in the power management control/ status (pmcsr) register is set. (the pmcsr is described in section 8.1.21, power management control/status register (pmcsr) on page 64 .) 4.3.2.1 interesting packet event in the power-down state, the 82559 is capable of recognizing interesting packets. the 82559 supports pre-defined and programmable packets that can be defined as any of the following: ? arp packets (with multiple ip addresses) ? direct packets (with or without type qualification) ? magic packet* ? neighbor discovery multicast address packet (arp in ipv6 environment) ? netbios over tcp/ip (nbt) query packet (under ipv4) ? internetwork package exchange* (ipx) diagnostic packet ? tco packet this allows the 82559 to handle various packet types. in general, the 82559 supports programmable filtering of any packet in the first 128 bytes. power state link 82559 functionality d0u dont care ? power-up state ? pci slave access d0a valid full functionality at full power and wake on invalid link invalid full functionality at full power and wake on valid link d1 valid ? wake on interestin g packets and link invalid ? pci confi g uration access invalid ? wake on link valid ? pci confi g uration access d2 valid same functionality as d1 (link valid) invalid detection for valid link and no link integrity d3 (with power) valid same functionality as d1 (link valid) invalid detection for valid link and no link integrity dx (x>0 without pme#) dont care no wake-up functionality note : if the tco bit is set in the eeprom, the 82559 will not disable the link function and will consume power as in the d2 state.
82559 networking silicon 32 datasheet when the 82559 is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. the only exception is the magic packet, which is scanned for the entire frame. the 82559 will classify the incoming packets as one of the following categories: ? no match. the 82559 discards the packet and continues to process the incoming packets. ? tco packet. the 82559 implements perfect filtering of tco packets. after a tco packet is processed, the 82559 is ready for the next incoming packet. there are two possible system environments: tco controller on the smb . the entire tco packet is transferred to the tco controller. system without tco controller . tco packets are treated as any other wake-up packet and may assert the pme# signal if configured to do so. ? wake-up packet. the 82559 is capable of recognizing and storing the first 128 bytes of a wake-up packet. if a wake-up packet is larger than 128 bytes, its tail is discarded by the 82559. after the system is fully powered-up, software has the ability to determine the cause of the wake-up event via the pmdr and dump the stored data to the host memory. magic packets are an exception. the magic packets may cause a power management event and set an indication bit in the pmdr; however, it is not stored by the 82559 for use by the system when it is woken up. 4.3.2.2 link status change event the 82559 link status indication circuit is capable of issuing a pme on a link status change from a valid link to an invalid link condition or vice versa. the 82559 reports a pme link status event in all power states. the pme# signal is gated by the pme enable bit in the pmcsr and the csma configure command, which is described in the 10/100 mbit family software developers manual . 4.4 cardbus power management the cardbus power management proposal differs from the pci power management specification in the following manner: ? the pme# signal is replaced by cstschg which is an active high output signal. ? an auxiliary power source, v aux , is supplied on the same v cc pins. ? an auxiliary power source bit in the pmc register must be set. ? the pci clock signal and the pci reset signal are guaranteed to be kept low in the b3 state. in addition, the 82559 also meets the cardbus requirement for current consumption less than 70 ma in the d0u state. 4.5 wake on lan (preboot wake-up) when the 82559 is drawing power from an auxiliary power source (v aux ), it can support the same preboot wake on lan (wol) capabilities as the 82558 device. the 82559 enters wol mode after the following events occur: ? an altrst# is completed. ? the 82559 reads the eeprom and the wol bit is set.
networking silicon 82559 datasheet 33 when the 82559 is in wol mode: ? the 82559 scans incoming packets for a magic packet. when it receives a magic packet, the 82559 asserts the pme# signal (until cleared) and the cstschg signal for 52 ms. ? the activity led changes its functionality to indicates that the received frame passed individual address (ia) filtering or broadcast filtering. ? the pci configuration registers are accessible to the host. ? software should not attempt to access the flash. the 82559 switches from wol mode to the d0a power state following a setup of the memory or i/o base address registers in the pci configuration space. while the 82559 is in the d0u, d1, d2, or d3 power state, if the 82559 receives a magic packet, it issues a positive pulse for approximately 52 ms on the cstschg pin. for pci systems and in designs that support the 3-pin header standard, the cstschg pin acts as the wol signal. 4.6 parallel flash/modem interface the 82559s parallel interface is used for flash interface only or modem interface only. the 82559 supports a glueless interface to an 8-bit wide, 128 kbyte, parallel memory device. the parallel local port is multiplexed with a modem interface in a lan/modem combination card. the flash (or boot prom) is read from or written to whenever the host cpu performs a read or a write operation to a memory location that is within the flash mapping window. all accesses to the flash, except read accesses, require the appropriate command sequence for the device used. (refer to the specific flash data sheet for more details on reading from or writing to the flash device.) the accesses to the flash are based on a direct decode of cpu accesses to a memory window defined in either the 82559 flash base address register (pci configuration space at offset 18h) or the expansion rom base address register (pci configuration space at offset 30h). the 82559 asserts control to the flash when it decodes a valid access. the 82559 supports an external flash memory (or boot prom) of up to 128 kbyte. the expansion rom address can be separately disabled by setting the corresponding bit in the eeprom, word ah. note: flash accesses must always be assembled or disassembled by the 82559 whenever the access is greater than a byte-wide access. due to slow access times to a typical flash and to avoid violating pci bus holding specifications (no more than 16 wait states inserted for any cycles that are not system initiation cycles), the maximum data size is either one word or one byte for a read operation and one byte only for a write operation. 4.7 serial eeprom interface the serial eeprom stores configuration data for the 82559 and is a serial in/serial out device. the 82559 supports a either a 64 register or 256 register size eeprom and automatically detects the eeproms size. a 256 word eeprom device is required for a cardbus system and contains the cis information. a 256 word eeprom device is also required for a tco enabled system in order to hold the heartbeat packet. the eeprom should operate at a frequency of at least 1 mhz.
82559 networking silicon 34 datasheet all accesses, either read or write, are preceded by a command instruction to the device. the address field is six bits for a 64 register eeprom or eight bits for a 256 register eeprom. the end of the address field is indicated by a dummy zero bit from the eeprom, which indicates the entire address field has been transferred to the device. an eeprom read instruction waveform is shown in the figure below. the 82559 may also use the eeprom for heartbeat packet transmission (systems without a tco controller are also supported). in these designs, the eeprom is accessed through time windows autonomously by the 82559 hardware. during these time windows, the 82559 will respond with a pci retry to both eeprom and flash accesses. the 82559 performs an automatic read of five words (0h, 1h, 2h, ah, and dh) of the eeprom after the de-assertion of reset. it may read six more words (bh, ch, fbh, fch, fdh, and feh) if the modem bit is set in the eeprom (word ah, bit 0). figure 11. 64-word eeprom read instruction waveform a 1 a 0 eecs eesk eedi eedo a 5 a 4 a 2 d 15 d 0 read op code a 3 a 1 a 0
networking silicon 82559 datasheet 35 the 82559 eeprom format is shown below in figure 12 . note that word ah contains several configuration bits. bits from word ah, fbh through feh, and certain bits from word dh are described as follows: word1514131211109876543210 0h ia byte 2 ia byte 1 1h ia byte 4 ia byte 3 2h ia byte 6 ia byte 5 ah sig id 0b bd rev id alt id dpd wol 00b wmr stb ena mdm bh subsystem id ch subsystem vendor id dh 0000b hb packet pointer smb address field/eeprom cis pointer fbh modem vendor id fch modem device id fdh modem program interface (02) modem revision number (00) feh modem power dissipation (d0-d3) modem power consumption (d0-d3) figure 12. 82559 eeprom format table 1. eeprom words field descriptions bits name description word ah, 15:14 signature the signature field is a signature of 01b, indicating to the 82559 that there is a valid eeprom present. if the signature field is not 01b, the other bits are ignored and the default values are used. word ah, 13 id the id bit indicates how the subsystem id and subsystem vendor id fields are used as described in section 8.1.12, pci subsystem vendor id and subsystem id registers on page 61 . default value is 0b. word ah, 12 reserved this bit is reserved and should be set to 0b. word ah, 11 boot disable the boot disable bit disables the expansion rom base address register (pci configuration space, offset 30h) when it is set. default value is 0b. word ah, 10:8 revision id these three bits are used as the three least significant bits of the device revision, if bits 15, 14, and 13 equal 011b and the id was set as described in section 8.1.12, pci subsystem vendor id and subsystem id registers on page 61 . the default value depends on the silicon revision (for example, the 82559 c-steps revision id is 09h). word ah, 7 82559 b-step this bit is reserved and should be set to 1b. 82559 c-step alternate id this bit is used in conjunction with the signature field and the id bit to help define the device id. when bit 7 equals 1b, the device id is 1229h and the device is compatible to previous steppings of the 82559. when bit 7 equals 0b, the lan function reports a device id of 1029h and the device is not compatible with the 82559. details regarding the 82559 id programming are described in section 8.1.12, pci subsystem vendor id and subsystem id registers on page 61 .
82559 networking silicon 36 datasheet note: the ia read from the eeprom is used by the 82559 until an ia setup command is issued by software. the ia defined by the ia setup command overrides the ia read from the eeprom. 4.8 10/100 mbps csma/cd unit the 82559 csma/cd unit implements both the ieee 802.3 ethernet 10 mbps and ieee 802.3u fast ethernet 100 mbps standards. it performs all the csma/cd protocol functions such as transmission, reception, collision handling, etc. the 82559 csma/cd unit interfaces the internal phy unit through a standard media independent interface (mii), as specified by ieee 802.3, chapter 22. this is a 10/100 mbps mode in which the data stream is nibble-wide and the serial clocks run at either 25 or 2.5 mhz. word ah, 6 deep power down this bit either enables or disables deep power down in the d2 or d3 states when pme is disabled: 0 deep power down is enabled in d3 state if pme-disabled 1 deep power down disabled in d3 state when pme-disabled. note: when using the 82559s alert capability, the deep power down capability should be disabled. alert devices will not be able to transmit or receive on the smbus if the device is in a deep power down mode. word ah, 5 wake on lan the wol bit sets the 82559 into wol mode. when in this mode the 82559 reads three additional words from the eeprom, word addresses 0h, 1h, and 2h. these words are expected to hold the mac individual address. after reading these words the 82559 wakes the system by asserting pme# when a wake-up packet is received. default value is 0b. word ah, 4:3 reserved these are reserved and should be set to 00b. word ah, 2 word ah, 1 standby enable the standby enable bit enables the 82559 to enter standby mode. when this bit equals 1b, the 82559 is able to recognize an idle state and can enter standby mode (some internal clocks are stopped for power saving purposes). the 82559 does not require a pci clock signal in standby mode. if this bit equals 0b, the idle recognition circuit is disabled and the 82559 always remains in an active state. thus, the 82559 will always request pci clk using the clockrun mechanism. word ah, 0 modem if this bit equals 0b, the design is a single function design (lan function) only. if this bit equals 1b, a modem is attached on the 82559 local parallel port. word dh, 11:8 heartbeat packet pointer this field of bits contains the location of the heartbeat packet within the eeprom. the pointers are expressed in a granularity of 16 words. a value of 0 is used as a null pointer. word, dh, 7:0 smb address field/eeprom cis pointer this field of bits is a multiplexed function field. in a pci system, it acts as an smb address field (7-bit field). when this field is used as the smb address field, bit 7 equals 0b. in a cardbus system, this field is used for cis pointers. when this field is used as the eeprom cis pointer, it contains two 4-bit pointers that point to the location of the cis information within the eeprom. the pointers are expressed in a granularity of 16 words. a value of 0 is used as a null pointer. the ethernet cis pointer resides in bits 3:0 and the modem cis pointer resides in bits 7:4. words fbh - feh modem configuration parameters these word fields hold the modem configuration parameters are loaded to the pci configuration space. a combination lan/modem card requires a 256-word eeprom. table 1. eeprom words field descriptions bits name description
networking silicon 82559 datasheet 37 4.8.1 full duplex when operating in full duplex mode the 82559 can transmit and receive frames simultaneously. transmission starts regardless of the state of the internal receive path. reception starts when the internal phy detects a valid frame on the receive differential pair of the phy. the 82559 operates in either half duplex mode or full duplex mode. for proper operation, both the 82559 csma/cd module and the phy unit must be set to the same duplex mode. the csma duplex mode is set by the 82559 configure command or forced by automatically tracking the mode in the phy unit. the phy duplex mode is set either by auto-negotiation or, if auto-negotiation is disabled, by setting the full duplex bit in the management data interface (mdi) register 0, bit 8. by default, the internal phy unit advertises full duplex ability in the auto-negotiation process regardless of the duplex setting of the csma unit. the csma configuration should match the result of the auto- negotiation. the selection of duplex operation (full or half) and flow control is done in two levels: mac and phy. the mac duplex selection is done only through csma configuration mechanism (in other words, the configure command from software). 4.8.2 flow control the 82559 supports ieee 802.3x frame based flow control frames only in both full duplex and half duplex switched environments. the 82559 flow control feature is not intended to be used in shared media environments. flow control is optional in full duplex mode and can be selected through software configuration. there are three modes of flow control that can be selected: frame based transmit flow control, frame based receive flow control, and none. the phy units duplex and flow control enable can be selected using nway* auto-negotiation algorithm or through the management data interface. 4.8.3 address filtering modifications the 82559 can be configured to ignore one bit when checking for its individual address (ia) on incoming receive frames. the address bit, known as the upper/lower (u/l) bit, is the second least significant bit of the first byte of the ia. this bit may be used, in some cases, as a priority indication bit. when configured to do so, the 82559 passes any frame that matches all other 47 address bits of its ia, regardless of the u/l bit value. this configuration only affects the 82559 specific ia and not multicast, multi-ia or broadcast address filtering. the 82559 does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit.
82559 networking silicon 38 datasheet 4.8.4 vlan support the 82559 supports the vlan standard currently being defined by the ieee 802.1 committee. all vlan flows will be implemented by software. the 82559 supports the reception of long frames, specifically frames longer than 1518 bytes, including the crc, if software sets the long receive ok bit in the configuration command (described in the 10/100 mbit family software developers manual ). otherwise, long frames are discarded. 4.9 media independent interface (mii) management interface the mii management interface allows the cpu to control the phy unit via a control register in the 82559. this allows the software driver to place the phy in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode. this structure allows the 82559 to query the phy unit for status of the link. this register is the mdi control register and resides at offset 10h in the 82559 csr. (the mdi registers are described in detail in section 10.0, phy unit registers on page 85 .) the cpu writes commands to this register and the 82559 reads or writes the control/status parameters to the phy unit through the mdi register. although the82559 follows the mii format, the mi bus is not accessible on external pins.
networking silicon 82559 datasheet 39 5.0 82559 physical layer functional description 5.1 100base-tx phy unit 5.1.1 100base-tx transmit clock generation a 25 mhz crystal or a 25 mhz oscillator is used to drive the phy units x1 and x2 pins. the phy unit derives its internal transmit digital clocks from this crystal or oscillator input. the internal transmit clock signal is a derivative of the 25 mhz internal clock. the accuracy of the external crystal or oscillator must be 0.0005% (50 ppm). 5.1.2 100base-tx transmit blocks the transmit subsection of the phy unit accepts nibble-wide data from the csma/cd unit. the transmit subsection passes data unconditionally to the 4b/5b encoder. the 4b/5b encoder accepts nibble-wide data (4 bits) from the csma unit and compiles it into 5- bit-wide parallel symbols. these symbols are scrambled and serialized into a 125 mbps bit stream, converted by the analog transmit driver into a mlt-3 waveform format, and transmitted onto the unshielded twisted pair (utp) or shielded twisted pair (stp) wire. 5.1.2.1 100base-tx 4b/5b encoder the 4b/5b encoder complies with the ieee 802.3u 100base-tx standard. four bits are encoded according to the transmit 4b/5b lookup table. the lookup table matches a 5-bit code to each 4-bit code. the table below illustrates the 4b/5b encoding scheme associated with the given symbol. table 2. 4b/5b encoder symbol 5b symbol code 4b nibble code 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 a 10110 1010 b 10111 1011 c 11010 1100
82559 networking silicon 40 datasheet 5.1.2.2 100base-tx scrambler and mlt-3 encoder data is scrambled in 100base-tx in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. the scrambler logic accepts 5 bits from the 4b/5b encoder block and presents the scrambled data to the mlt-3 encoder. the phy unit implements the 11-bit stream cipher scrambler as adopted by the ansi xt3t9.5 committee for utp operation. the cipher equation used is: x[n] = x[n-11] + x[n-9] (mod 2) the encoder receives the scrambled non-return to zero (nrz) data stream from the scrambler and encodes the stream into mlt-3 for presentation to the driver. mlt-3 is similar to nrzi coding, but three levels are output instead of two. there are three output levels: positive, negative and zero. d 11011 1101 e 11100 1110 f 11101 1111 i 11111 inter packet idle symbol (no 4b) j 11000 1st start of packet symbol 0101 k 10001 2nd start of packet symbol 0101 t 01101 1st end of packet symbol r 00111 2nd end of packet symbol and flow control v 00000 invalid v 00001 invalid v 00010 invalid v 00011 invalid h 00100 invalid v 00101 invalid v 00110 invalid v 01000 invalid v 01100 invalid v 10000 phy based flow control v 11001 invalid table 2. 4b/5b encoder symbol 5b symbol code 4b nibble code
networking silicon 82559 datasheet 41 when an nrz 0 arrives at the input of the encoder, the last output level is maintained (either positive, negative or zero). when an nrz 1 arrives at the input of the encoder, the output steps to the next level. the order of steps is negative-zero-positive-zero which continues periodically. 5.1.2.3 100base-tx transmit framing the phy unit does not differentiate between the fields of the mac frame containing preamble, start of frame delimiter, data and cyclic redundancy check (crc). the phy unit encodes the first byte of the preamble as the jk symbol, encodes all other pieces of data according to the 4b/ 5b lookup table, and adds the tr code after the end of the packet. the phy unit scrambles and serializes the data into a 125 mbps stream, encodes it as mlt-3, and drives it onto the wire. 5.1.2.4 transmit driver the transmit differential pair lines are implemented with a digital slope controlled current driver that meets the tp-pmd specifications. current is sinked from the isolation transformer by the tdp and tdn pins. the conceptual transmit differential waveform for 100 mbps is illustrated in the following figure. figure 13. nrz to mlt-3 encoding diagram clock nrz nrz1 mlt-3 1100 0 11 0 1100 0 11 0 1100 0 11 0 figure 14. conceptual transmit differential waveform (v tdp -v tdn ) +1v 0v -1v t
82559 networking silicon 42 datasheet the magnetics module that is external to the phy unit converts i tdp and i tdn to the 2.0 v pp , as required by the tp-pmd specification. the same magnetics used for 100base-tx mode should also work in 10base-t mode. the following is a list of current magnetics modules available from several vendors: 5.1.3 100base-tx receive blocks the receive subsection of the phy unit accepts 100base-tx mlt-3 data on the receive differential pair. due to the advanced digital signal processing design techniques employed, the phy unit will accurately receive valid data from category-5 (cat5) utp and type 1 stp cable of length well in excess of 100 meters. 5.1.3.1 adaptive equalizer the distorted mlt-3 signal at the end of the wire is restored by the equalizer. the equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior data dependent jitter performance. 5.1.3.2 receive clock and data recovery the clock recovery circuit uses advanced digital signal processing technology to compensate for various signal jitter causes. the circuit recovers the 125 mhz clock and data and presents the data to the mlt-3 decoder. 5.1.3.3 mlt-3 decoder, descrambler, and receive digital section the phy unit first decodes the mlt-3 data; afterwards, the descrambler reproduces the 5b symbols originated in the transmitter. the descrambling is based on synchronization to the transmit 11-bit linear feedback shift register (lfsr) during idle. the data is decoded at the 4b/5b decoder. once the 4b symbols are obtained, the phy unit outputs the receive data to the csma unit. 5.1.3.4 100base-tx receive framing the phy unit does not differentiate between the fields of the mac frame containing preamble, start of frame delimiter, data and crc. during 100 mbps reception, the phy unit differentiates between the idle condition ("l" symbols on the wire) and the preamble or start of frame delimiter. when two non-consecutive bits are 0b within 10 bits (125 mbps 5b data coding) the phy unit immediately asserts carrier sense. when the jk symbols (11000, 10001) are fully recognized, the phy unit provides the received data to the csma unit. if the jk symbol is not recognized (false carrier sense), the carrier sense is immediately de-asserted and a receive error is indicated. table 3. magnetics modules vendor model/type 100base-tx 10base-t delta lf8200a yes yes pulse engineering pe-68515 yes yes pulse engineering h1012 yes yes
networking silicon 82559 datasheet 43 5.1.3.5 100base-tx receive error detection and reporting in 100base-tx mode, the phy unit can detect errors in receive data in a number of ways. any of the following conditions is considered an error: ? link integrity fails in the middle of frame reception. ? the start of stream delimiter (ssd) jk symbol is not fully detected after idle. ? an invalid symbol is detected at the 4b/5b decoder. ? idle is detected in the middle of a frame (before tr is detected). when any of the above error conditions occurs, the phy unit immediately asserts its receive error indication to the csma unit. the receive error indication is held active as long as the receive error condition persists on the receive pair. 5.1.4 100base-tx collision detection 100base-tx collisions in half duplex mode only are detected similarly to 10base-t collision detection, via simultaneous transmission and reception. 5.1.5 100base-tx link integrity and auto-negotiation solution the 82559 auto-negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. auto-negotiation is widely described in ieee specification 802.3u, clause 28. the phy unit supports 10base-t half duplex, 10base-t full duplex, 100base-tx half duplex, and 100base-tx full duplex. the phy unit has two physical media attachment (pma) technologies with its link integrity function, 10base-t and 100base-tx. 5.1.5.1 link integrity in 100base-tx, the link integrity function is determined by a stable signal status coming from the tp-pmd block. signal status is asserted when the pmd detects breaking squelch energy and the right bit error rate according to the ansi specification. 5.1.5.2 auto-negotiation the phy unit fully supports ieee 802.3u, clause 28. the technology, 10base-t or 100base- tx, is determined by the auto-negotiation result. speed and duplex auto-select are functions of auto-negotiation. however, these parameters may be manually configured via the mii management interface (mdi registers). 5.1.6 auto 10/100 mbps speed selection the mac may either allow the phy unit to automatically select its operating speed or force the phy into 10 mbps or 100 mbps mode. the management data interface (mdi) can control the phy unit speed mode.
82559 networking silicon 44 datasheet the phy unit auto-select function determines the operation speed of the media based on the link integrity pulses it receives. if no fast link pulses (flps) are detected and normal link pulses (nlps) are detected, the phy unit defaults to 10 mbps operation. if the phy unit detects a speed change, it dynamically changes its transmit clock and receive clock frequencies to the appropriate value. this change takes a maximum of five milliseconds. 5.2 10base-t functionality 5.2.1 10base-t transmit clock generation the 20 mhz and 10 mhz clocks needed for 10base-t are synthesized from the external 25 mhz crystal or oscillator. the phy unit provides the transmit clock and receive clock to the internal mac at 2.5 mhz. 5.2.2 10base-t transmit blocks 5.2.2.1 10base-t manchester encoder after the 2.5 mhz clocked data is serialized in a 10 mbps serial stream, the 20 mhz clock performs the manchester encoding. the manchester code always has a mid-bit transition. if the value is 1b then the transition is from low to high. if the value is 0b then the transition is from high to low. the boundary transition occurs only when the data changes from bit to bit. for example, if the value is 10b, then the change is from high to low; if 01b, then the change is from low to high. 5.2.2.2 10base-t driver and filter since 10base-t and 100base-tx have different filtration needs, both filters are implemented inside the chip. this allows the two technologies to share the same magnetics. the phy unit supports both technologies through one pair of td pins and by externally sharing the same magnetics. in 10 mbps mode, the phy unit begins transmitting the serial manchester bit stream within 3 bit times (300 nanoseconds) after the mac asserts txen. in 10 mbps mode the line drivers use a pre- distortion algorithm to improve jitter tolerance. the line drivers reduce their drive level during the second half of wide (100ns) manchester pulses and maintain a full drive level during all narrow (50ns) pulses and the first half of the wide pulses. this reduces line overcharging during wide pulses, a major source of jitter. 5.2.3 10base-t receive blocks 5.2.3.1 10base-t manchester decoder the phy unit performs manchester decoding and timing recovery when in 10 mbps mode. the manchester-encoded data stream is decoded from the rd pair to separate receive clock and receive data from the differential signal. this data is transferred to the csma unit at 2.5 mhz/ nibble. the high-performance circuitry of the phy unit exceeds the ieee 802.3 jitter requirements.
networking silicon 82559 datasheet 45 5.2.3.2 10base-t twisted pair ethernet (tpe) receive buffer and filter in 10 mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. the filter is implemented inside the phy unit for supporting single magnetics that are shared with the 100base-tx side. the input differential voltage range for the twisted pair ethernet (tpe) receiver is greater than 585 mv and less than 3.1 v. the tpe receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10base-t standard. the following line activity is determined to be inactive and is rejected: ? differential pulses of peak magnitude less than 300 mv ? continuous sinusoids with a differential amplitude less than 6.2 v pp and frequency less than 2 mhz ? sine waves of a single cycle duration starting with 0 or 180 phase that have a differential amplitude less than 6.2 v pp and a frequency of at least 2 mhz and not more than 16 mhz. these single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 nanoseconds) of silence. all other activity is determined to be either data, link test pulses, auto-negotiation fast link pulses, or the idle condition. when activity is detected, the carrier sense signal is asserted to the mac. 5.2.3.3 10base-t error detection and reporting in 10 mbps mode, the phy unit can detect errors in the receive data. the following condition is considered an error: the receive pairs voltage level drops to the idle state during reception before the end-of-frame bit is detected (250 nanoseconds without mid-bit transitions). 5.2.4 10base-t collision detection collision detection in 10 mbps mode is indicated by simultaneous transmission and reception. if the phy unit detects this condition, it asserts a collision indication to the csma/cd unit. 5.2.5 10base-t link integrity the link integrity in 10 mbps works with link pulses. the phy unit senses and differentiates those link pulses from fast link pulses and from 100base-tx idles. the 10 mbps link pulses or normal link pulses are driven in the transmit differential pair line but are 100 ns wide and have levels from 0 v to 5 v. the link beat pulse is also used to determine if the receive pair polarity is reversed. if it is, the polarity is corrected internally. 5.2.6 10base-t jabber control function the phy unit contains a jabber control function that inhibits transmission after a specified time window when enabled. in 10 mbps mode, the jabber timer is set to a value between 26.2 ms and 39 ms. if the phy unit detects continuous transmission that is greater than this time period, it prevents further transmissions from onto the wire until it detects that the mac transmit enable signal has been inactive for at least 314 ms.
82559 networking silicon 46 datasheet 5.2.7 10base-t full duplex the phy unit supports 10 mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. this allows the phy unit to transmit and receive simultaneously, achieving up to 20 mbps of network bandwidth. the configuration can be achieved through auto-negotiation. full duplex should only be used in point-to-point connections (no shared media). 5.3 auto-negotiation functionality the phy unit supports auto-negotiation. auto-negotiation is an automatic configuration scheme designed to manage interoperability in multifunctional lan environments. it allows two stations with n different modes of communication to establish a common mode of operation. at power- up, auto-negotiation automatically establishes a link that takes advantage of an auto-negotiation capable device. an auto-negotiation capable device can detect and automatically configure its port to take maximum advantage of common modes of operation without user intervention or prior knowledge by either station. the possible common modes of operation are: 100base-tx, 100base-tx full duplex, 10base-t, and 10base-t full duplex. 5.3.1 description auto-negotiation selects the fastest operating mode (in other words, the highest common denominator) available to hardware at both ends of the cable. a phys capability is encoded by bursts of link pulses called fast link pulses (flps). connection is established by flp exchange and handshake during link initialization time. once the link is established by this handshake, the native link pulse scheme resumes (that is, 10base-t or 100base-tx link pulses). a reset or management renegotiate command (through the mdi interface) will restart the process. to enable auto-negotiation, bit 12 of the mdi control register must be set. if the phy unit cannot perform auto-negotiation, it will set this bit to a 0 and determine the speed using parallel detection. the phy unit supports four technologies: 100base-tx full and half duplex and 10base-t full and half duplex. since only one technology can be used at a time (after every re-negotiate command), a prioritization scheme must be used to ensure that the highest common denominator ability is chosen. each bit in this table is set according to what the phy is capable of supporting. in the case of the 82559s phy unit, bits 0, 1, 2, 3, and 5 (10base-t, 10base-t full duplex, 100base-tx, 100base-tx full duplex and pause [frame based flow control], respectively) are set. to detect the correct technology, the two register fields, technology ability and technology priority, should be anded together to obtain the highest common denominator. this value should then be used to map into a priority resolution table used by the mac driver to use the appropriate technology. 5.3.2 parallel detect and auto-negotiation the phy unit automatically determines the speed of the link either by using parallel detect or auto-negotiation. upon a reset, a link status fail, or a negotiate/re-negotiate command, the phy unit inserts a long delay during which no link pulses are transmitted. this period, known as force_fail, insures that the phy units link partner has gone into a link fail state before auto- negotiation or parallel detection begins. thus, both sides (phy unit and phy units link partner)
networking silicon 82559 datasheet 47 will perform auto-negotiation or parallel detection with no data packets being transmitted. connection is then established either by flp exchange or parallel detection. the phy unit will look for both flps and link integrity pulses. the following diagram illustrates this process. 5.4 led description the phy unit supports three led pins to indicate link status, network activity and network speed. each pin can source 10 ma. ? link : this led is off until a valid link has been detected. after a valid link has been detected, the led will remain on (active-low). ? activity : this led blinks on and off when activity is detected on the wire. ? speed : this led will be on if a 100base-tx link is detected and off if a 10base-t link is detected. if the link fails while in auto-negotiation, this led will keep the last valid link state. if 100base-tx link is forced this led will be on, regardless of the link status. this led will be of if the 10base-t link is forced, regardless of the link status. mdi register 27 in section 10.3.12, register 27: phy unit special control bit definitions on page 92 details the information for led function mapping and support enhancements. figure 15. auto-negotiation and parallel detect force_fail ability detect either by parallel detect or auto- negotiation. 10base-t or 100base-tx link ready flp capable link pass parallel detection auto-negotiation look at link pulse; auto-negotiation capable = 0 auto-negotiation capable = 1 ability match auto-negotiation complete bit set
82559 networking silicon 48 datasheet figure 16 provides possible schematic diagrams for configurations using two and three leds. figure 16. two and three led schematic diagram liled actled vcc speedled liled actled speedled 82559er vcc
networking silicon 82559 datasheet 49 6.0 82559 modem functionality the local port mimics the standard 8-bit interface of a modem to the host system and emulates a 16550 universal asynchronous receiver/transceiver (uart) modem interface. the modem interface includes the following: ? 8-bit data bus: fld[7:0] ? control signals: aen (flcs#), mcntsm# (fla[12]), mint (fla[11]), mring# (fla[10]), mrst (fla[9]), rd# (floe#), and wr# (flwe#) ? 4 address lines 6.1 pci address mapping to the modem the modem can be accessed by the pci bus through either i/o or memory mapping. 6.2 modem read and write cycles basic read/write cycles to the modem device are shown in the figure below. 6.3 modem and preboot extension environment coexistence the 82559 c-step local bus interface supports either a flash device or modem without external support. in addition, the 82559 can also support both devices concurrently on the bus. support is provided through the use of the security asic chip select (cfcs#) pin by using it in conjunction with the flash chip select (flcs#) signal to enable the target device. 6.3.1 programming details for designs that use both flash and modem devices, the 82559 c-step supports the coexistence of bootrom accesses (for preboot extension environment [pxe] code) and modem: 1. set the eeproms mdm bit. figure 17. modem read/write cycles modem aen ( cs# ) modem addrsess modem data in / out modem we# / rd# modem iochrdy
82559 networking silicon 50 datasheet 2. clear the bd bit in the eeprom. this enables both the modem and boot rom. this allows the boot enable bit in the expansion bar to select which external device (modem or flash) is active on the local bus through the use of the cfcs# pin. after initialization, the 82559 c-step enables the flash on the local bus (in other words, the boot enable bit in the bar equals 1b) and the modem is disabled. following the execution of the boot code from the flash device, the enable bit is cleared, and the modem is enabled. the clearing of the boot enable bit causes the cfcs# pin to be de-asserted, enabling the modem, function 1 (modem) configuration space, to be available regardless of the state of the boot enable bit or cfcs#. 6.3.2 support circuitry an example of support circuitry is shown in figure 18 . when cfcs# is low, the modem is enabled; cfcs# is high, the flash device is enabled. figure 18. support circuitry example modem_cs# flash_cs# cfcs# ( modem_mode# ) flcs#
networking silicon 82559 datasheet 51 7.0 82559 tco functionality the 82559 supports management communication to reduce total cost of ownership (tco). it has a system management bus (smb) on which the 82559 is a slave device. the smb is used as an interface between the 82559 and a tco entity. the tco entity may be a dedicated tco controller, or it may be direct connection to a future integrated host controller. in the case of a direct connection to an integrated host controller, a larger eeprom of 256 words would be required if the heartbeat command is used. the sections below describe the 82559s functionality in the a system with a tco controller and a system without a tco controller. 7.1 system functionality with a tco controller when a tco controller accesses the 82559 through the smb, the bus operates as a half duplex channel. therefore, once the tco controller starts a transmit command or another execution command, it must complete it before responding to the smb alert (smbalrt) cause and vise versa. the 82559 functionality available through the smb is listed in the table below. d0 nominal operation : in the d0 power state, the 82559 can transfer tco packets to the tco controller. this feature is enabled by the set receive enable command from the tco controller. the tco packets are transferred to the 82559s memory structure, receive frame area (rfa); therefore, this feature requires software to be loaded and available receive resources. the 82559 suspends transmit and receive processes and sets the tco request bit in the tco state register. afterwards, it transfers the tco packet back to the tco controller through the smb and reclaims receive memory structures that are occupied by the tco packet, eliminating the need for software intervention in the process. finally, the 82559 increments the receive tco statistic counter, clears the tco request bit and resumes normal operation. the 82559 always increments the receive tco counter following the reception of a tco packet. note: traffic between the 82559 and the tco controller is limited by the smb speed and the tco controller latency. for example, for a system with a 100 khz clock on the smb, the bandwidth may be as low as 50 kbps, which is a reception rate of approximately 100 packets per second for 64-byte packets. transmit command during nominal operation power state tco controller functionality d0 nominal ? transmit ? set receive tco packets ? receive tco packets ? read 82559 status ? force tco mode dx (x > 0) ? d0 functionalit y ? read phy re g isters force tco mode ? dx functionalit y ? confi g ure commands ( confi g uration, individual address, multicast, load microcode ) ? read/write phy re g isters
82559 networking silicon 52 datasheet the 82559 completes the following process for the during nominal operation of the transmit command in tco mode. 1. the 82559 completes the current transmit dma. 2. the 82559 sets the tco request bit in the tco state register. 3. the 82559 responds to the tco controllers transmit request. 4. upon completion of the tco transmit dma, the 82559 increments the transmit tco statistic counter. 5. upon completion of the transmit operation, the 82559 increments the nominal transmit statistic counters and clears the tco request bit in the tco state register. 6. the 82559 resumes its normal transmit flow. during the this time, the receive flow is not affected. receive tco packets the 82559 supports receive flow towards the tco controller. the 82559 can transfer either tco packets or packets that pass mac address filtering according to its configuration and mode of operation. if the 82559 is configured to transfer only tco packets, it supports ethernet type ii packets with optional vlan tagging. read 82559 status (power management and link state) the tco controller is capable of reading the 82559s power state and link status. following a status change the 82559 issues an smb alert and the tco entity reads the new power state. set force tco mode the tco controller can set the 82559 into the force tco mode. the 82559 is set back to the nominal operation following a pci rst# or altrst#. after the transition from normal operation to tco mode, the 82559 aborts transmit and receive operations and clears its memory structures. the tco may configure the 82559 before it starts transmit and receive operations if required. caution : the force tco is a destructive command. it causes the 82559 to lose its memory structures. also, in force tco mode, the 82559 ignores pci cycles. therefore, it is highly recommended to use this command by the tco controller at system emergency only. dx (x>0) : when the 82559 is in a low power state (d1, d2, or d3), it may receive tco packets directly to the tco controller. tco packet reception is enabled by setting the receive enable command from the tco controller. although tco packets can match other wake-up filters, once it is identified as a tco packet, no further matching is performed. when tco reception is disabled, a tco packet may cause a power management event if configured to so by the load wake-up packet command. force tco mode : when the 82559 is in the force tco mode, it may receive packets directly to the tco controller. tco packet reception and filtering is controlled by the set receive enable command from the tco controller. after receiving a tco packet, the 82559 increments its nominal receive statistic counters as well as the receive tco counter. configuration commands while the 82559 is in the force tco mode it supports the configure csma, individual address setup, multicast setup, load microcode commands and allows read/write access to the phy registers.
networking silicon 82559 datasheet 53 7.2 system functionality without a tco controller this section describes the 82559 functionality when it is connected on the smb directly to an integrated host controller. receive functionality - in the power-up state, the 82559 transfers tco packets to the host as any other packet. these packets include a new status indication bit in the 82559s receive frame descriptor (rfd) status and have a specific port number indicating tco packet recognition. in the power-down state, the tco packets are treated as a wake-up packets. the 82559 asserts the pme# signal and delivers the first 120 bytes of the packet to the host. transmit functionality - the 82559 supports the heartbeat (hb) transmission command from the smb interface. the send hb packet command includes a system health status issued by the integrated system controller. the 82559 computes a matched checksum and crc and will transmit the hb packet from its serial eeprom. the hb packet size and structure are not limited as long as it fits within the eeprom size. in this case, the eeprom size is 256 words to enable the storage of the hb packet (the first 64 words are used for driver specific data). note: on the smb, the send heartbeat packet command is not normally used in the d0 power state. the one exception in which it is used in the d0 state is when the system is hung. in normal operating mode, the heartbeat packets are transmitted through the 82559s software similar to other packets. 7.3 tco interface support for a tco controller is through a dedicated smb interface. the 82559 acts as a slave on the smb and supports data (smbd), clock (smbclk), and alert (smbalrt#) signals. the 82559 meets the 100 khz smb requirements according to the specification. it is also functional with an increased clock frequency of up to 1 mhz and still meets all required smb timings. a basic smb wave form diagram is shown in figure 19 . 7.3.1 smb alert signal (smbalrt#) the 82559 operates in slave mode on the smb during both read and write cycles. when the 82559 transmits data on the smb (receive packet), it issues the smbalrt# signal. in response to the smbalrt# activation, the host processes the interrupt. it accesses all smb devices simultaneously by an alert response address (ara) cycle. the device(s) that issued the smbalrt# signal acknowledges the cycle. if more than one device issued the smbalrt#, the highest priority (lowest address) device will win communication. only the winning device can de- asserts its smbalrt# signal. as a slave device, the 82559 signals the external tco controller using smbalrt#. the smbalrt# signal is activated for the following events: figure 19. smb session smbclk smbd msb r/w# addr ack ack ack ack cmd bc data start stop
82559 networking silicon 54 datasheet ? tco packet received ? low power state change ? phy read 7.3.2 alert response address (ara) cycle if a slave device needs to initiate a session, it should assert the smbalrt signal as follow: if the 82559 is not ready, it indicates this in one of two ways: 1. if the 82559s phy unit is in a low power state, the 82559 will not produce the acknowledge bit after its address appears on the bus. this forces the tco controller to stop the session and restart it. 2. if the 82559s phy unit is in nominal mode, the 82559 will pull-down the smbclk until it is ready. if the 82559 forces the smbclk for more then 25 ms, the tco controller should stop the transmission and restart it. figure 20. slave request for data transfer smbclk smbd ack msb ack 1 start stop smbalrt# the smbalrt# will rise onl y if an address match exists. msb 1
networking silicon 82559 datasheet 55 8.0 pci and cardbus configuration registers the 82559 acts as both a master and a slave on the pci bus. as a master, the 82559 interacts with the system main memory to access data for transmission or deposit received data. as a slave, some 82559 control structures are accessed by the host cpu to read or write information to the on-chip registers. the cpu also provides the 82559 with the necessary commands and pointers that allow it to process receive and transmit data. 8.1 function 0: lan (ethernet) pci configuration space the 82559 pci configuration space is configured as 16 dwords of type 0 configuration space header, as defined in the pci specification, revision 2.1. a small section is also configured according to its device specific configuration space. the configuration space header is depicted below in figure 21 . 8.1.1 pci vendor id and device id registers the vendor id and device id of the 82559 are both read only word entities. their values are: vendor id: 8086h device id: 1229h device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch csr memory mapped base address register 10h csr i/o mapped base address register 14h flash memory mapped base address register 18h reserved base address register 1ch reserved base address register 20h reserved base address register 24h reserved (pci)/cis pointer (cardbus) 28h subsystem id subsystem vendor id 2ch expansion rom base address register 30h reserved cap_ptr 34h reserved 38h max_lat min_gnt interrupt pin interrupt line 3ch power management capabilities next item ptr capability id dch reserved data power management csr e0h figure 21. pci configuration registers
82559 networking silicon 56 datasheet 8.1.2 pci command register the 82559 command register at word address 04h in the pci configuration space provides control over the 82559s ability to generate and respond to pci cycles . if a 0his written to this register, the 82559 is logically disconnected from the pci bus for all accesses except configuration accesses . the format of this register is shown in the figure below. note that bits three, five, seven, and nine are set to 0b. the table below describes the bits of the pci command register. figure 22. pci command register reserved serr# enable parity error response memory write and invalidate enable bus master enable memory space io space 0 0 0 0 10 15 0 1 2 3 4 5 6 7 8 9 table 4. pci command register bits bits name description 15:10 reserved these bits are reserved and should be set to 000000b. 8 serr# enable this bit controls a devices ability to enable the serr# driver. a value of 0b disables the serr# driver. a value of 1b enables the serr# driver. this bit must be set to report address parity errors. in the 82559, this bit is configurable and has a default value of 0b. 6 parity error control this bit controls a devices response to parity errors. a value of 0b causes the device to ignore any parity errors that it detects and continue normal operation. a value of 1b causes the device to take normal action when a parity error is detected. this bit must be set to 0b after rst# is asserted. in the 82559, this bit is configurable and has a default value of 0b. 4 memory write and invalidate enable this bit controls a devices ability to use the memory write and invalidate command. a value of 0b disables the device from using the memory write and invalidate enable command. a value of 1b enables the device to use the memory write and invalidate command. in the 82559, this bit is configurable and has a default value of 0b. 2 bus master this bit controls a devices ability to act as a master on the pci bus. a value of 0b disables the device from generating pci accesses. a value of 1b allows the device to behave as a bus master. in the 82559, this bit is configurable and has a default value of 0b. 1 memory space this bit controls a devices response to the memory space accesses. a value of 0b disables the device response. a value of 1b allows the device to respond to memory space accesses. in the 82559, this bit is configurable and its default value of 0b. 0 i/o space this bit controls a devices response to the i/o space accesses . a value of 0b disables the device response. a value of 1b allows the device to respond to i/o space accesses. in the 82559, this bit is configurable and the default value of 0b.
networking silicon 82559 datasheet 57 8.1.3 pci status register the 82559 status register is used to record status information for pci bus related events. the format of this register is shown in the figure below. note that bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. the pci status register bits are described in the table below. figure 23. pci status register 0 detected parit y error si g naled s y stem error received master abort received tar g et abort si g naled tar g et abort devsel timin g parit y error detected fast back to back ( tar g et ) capabilities list reserved 0 1 1 0 0 0 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 16 table 5. pci status register bits bits name description 31 detected parity error this bit indicates whether a parity error is detected. this bit must be asserted by the device when it detects a parity error, even if parity error handling is disabled (as controlled by the parity error response bit in the pci command register, bit 6). in the 82559, the initial value of the detected parity error bit is 0b. this bit is set until cleared by writing a 1b. 30 signaled system error this bit indicates when the device has asserted serr#. in the 82559, the initial value of the signaled system error bit is 0b. this bit is set until cleared by writing a 1b. 29 received master abort this bit indicates whether or not a master abort has occurred. this bit must be set by the master device when its transaction is terminated with a master abort. in the 82559, the initial value of the received master abort bit is 0b. this bit is set until cleared by writing a 1b. 28 received target abort this bit indicates that the master has received the target abort. this bit must be set by the master device when its transaction is terminated by a target abort. in the 82559, the initial value of the received target abort bit is 0b. this bit is set until cleared by writing a 1b. 27 signaled target abort this bit indicates whether a transaction was terminated by a target abort. this bit must be set by the target device when it terminates a transaction with target abort. in the 82559, this bit is always set to 0b. 26:25 devsel# timing these two bits indicate the timing of devsel#: 00b - fast 01b - medium 10b - slow 11b - reserved in the 82559, these bits are always set to 01b, medium.
82559 networking silicon 58 datasheet 8.1.4 pci revision id register the revision id is an 8-bit read only register with a default value of 08h for the 82559. the three least significant bits of the revision id can be overridden by the id and revision id fields in the eeprom ( section 4.7, serial eeprom interface on page 33 ). 8.1.5 pci class code register the class code register is read only and is used to identify the generic function of the device and, in some cases, specific register level programming interface. the register is broken into three byte size fields. the upper byte is a base class code and specifies the 82559 as a network controller, 2h. the middle byte is a subclass code and specifies the 82559 as an ethernet controller, 0h. the lower byte identifies a specific register level programming interface and the 82559 always returns a 0h in this field. 8.1.6 pci cache line size register in order for the 82559 to support the memory write and invalidate (mwi) command, the 82559 must also support the cache line size (cls) register in pci configuration space. the register supports only cache line sizes of 8 and 16 dwords. any value other than 8 or 16 that is written to the register is ignored and the 82559 does not use the mwi command. if a value other than 8 or 16 is written into the cls register, the 82559 returns all zeroes when the cls register is read. the figure below illustrates the format of this register. 24 parity error detected this bit indicates whether a parity error has been detected. this bit is set to 1b when the following three conditions are met: 1. the bus a g ent asserted perr# itself or observed perr# asserted. 2. the a g ent settin g the bit acted as the bus master for the operation in which the error occurred. 3. the parit y error response bit in the command re g ister ( bit 6 ) is set. in the 82559, the initial value of the parity error detected bit is 0b. this bit is set until cleared by writing a 1b. 23 fast back-to-back this bit indicates a devices ability to accept fast back-to-back transactions when the transactions are not to the same agent. a value of 0b disables fast back-to-back ability. a value of 1b enables fast back-to-back ability. in the 82559, this bit is read only and is set to 1b. 20 capabilities list this bit indicates whether the 82559 implements a list of new capabilities such as pci power management. a value of 0b means that this function does not implement the capabilities list. if this bit is set to 1b, the cap_ptr register provides an offset into the 82559 pci configuration space pointing to the location of the first item in the capabilities list. this bit is set only if the power management bit in the eeprom is set. 19:16 reserved these bits are reserved and should be set to 0000b. table 5. pci status register bits bits name description 76543210 000rwrw000 figure 24. cache line size register
networking silicon 82559 datasheet 59 note: bit 3 is set to 1b only if the value 00001000b (8h) is written to this register, and bit 4 is set to 1b only if the value of 00010000b (16h) is written to this register. all other bits are read only and will return a value of 0b on read. this register is expected to be written by the bios and the 82559 driver should not write to it. 8.1.7 pci latency timer the latency timer register is a byte wide register. when the 82559 is acting as a bus master, this register defines the amount of time, in pci clock cycles, that it may own the bus. 8.1.8 pci header type the header type register is a byte read only register. it is equal to 00h for a single function ethernet card and 80h for a combination ethernet and modem card. the value of the header type is set by the eeprom ( section 4.7, serial eeprom interface on page 33 ). in a dual function card, the os will read the next configuration registers bank at offset 100h. 8.1.9 pci base address registers one of the most important functions for enabling superior configurability and ease of use is the ability to relocate pci devices in address spaces. the 82559 contains three types of base address registers (bars). two are used for memory mapped resources, and one is used for i/o mapping. each register is 32 bits wide. the least significant bit in the bar determines whether it represents a memory or i/o space. the figures below show the layout of a bar for both memory and i/o mapping. after determining this information, power-up software can map the memory and i/o controllers into available locations and proceed with system boot. in order to do this mapping in a device independent manner, the base registers for this mapping are placed in the predefined header portion of configuration space. device drivers can then access this configuration space to determine the mapping of a particular device. figure 25. base address register for memory mapping base address 0 0 31 4321 prefetchable the prefetchable bit is set to 0 in 82559 devices ty p e 00 - locate anywhere in 32-bit address space 01 - locate below 1 mbyte 10 - locate anywhere in 64-bit address space 11 - reserved memory space indicator
82559 networking silicon 60 datasheet note: bit 0 in all base registers is read only and used to determine whether the register maps into memory or i/o space. base registers that map to memory space must return a 0b in bit 0. base registers that map to i/o space must return 1b in bit 0. base registers that map into i/o space are always 32 bits wide with bit 0 hard-wired to a 1b, bit 1 is reserved and must return 0b on reads, and the other bits are used to map the device into i/o space. the number of upper bits that a device actually implements depends on how much of the address space the device will respond to. for example, a device that wants a 1 mbyte memory address space would set the most significant 12 bits of the base address register to be configurable, setting the other bits to 0b. the 82559 contains bars for the control/status register (csr), flash, and expansion rom. 8.1.9.1 csr memory mapped base address register the 82559 requires one bar for memory mapping. software determines which bar, memory or i/o, is used to access the 82559 csr registers. the memory space for the 82559 csr memory mapped bar is 4 kbytes. the space is marked as not prefetchable and is mapped anywhere in the 32-bit memory address space. 8.1.9.2 csr i/o mapped base address register the 82559 requires one bar for i/o mapping. software determines which bar, memory or i/o, is used to access the 82559 csr registers. the i/o space for the 82559 csr i/o bar is 64 bytes. 8.1.9.3 flash memory mapped base address register the flash memory bar is a dword register. the 82559 physically supports a 128 kbyte flash device. in a cardbus system, the upper section of the memory mapped window (above the physical flash device) is used for cis information. the 82559 claims a window of 128 kbytes in cardbus mode and always claims a flash memory window, regardless of whether or not a flash device is connected. 8.1.9.4 expansion rom base address register the expansion rom has a memory space of 1 mbyte and its bar is a dword register that supports a 128 kbyte memory via the 82559 local bus. the expansion rom bar can be disabled by setting the boot disable bit of the eeprom (word ah, bit 11). if the boot disable bit is set, the 82559 returns a 0b for all bits in this address register, avoiding request of memory allocation for this space. in lan/modem combination designs using flash, this bit controls the state of the cfcs# signal (pin l7) and is cleared after the initial access of the expansion rom area. therefore, in a figure 26. base address register for i/o mapping base address 0 0 31 21 reserved i/o space indicator 1
networking silicon 82559 datasheet 61 lan/modem combination design, the cfcs# signal will be de-asserted (high) when the boot disable bit is not set in the eeprom and the rom enable bit is set in the expansion rom base address register. after the initial access to the expansion rom bar, the boot disable bit is cleared and cfcs# is asserted (low) enabling the modem to use the local bus. 8.1.10 base address registry summary the preceding description of the base address registers functions are summarized in the following table: 8.1.11 cardbus card information structure (cis) pointer the card information structure (cis) pointer is a dword hard coded read only register. it is meaningful only in a cardbus system (in a pci system it is zero). the cis pointer defines where the cis structure is mapped in the flash address space. 8.1.12 pci subsystem vendor id and subsystem id registers the subsystem vendor id field identifies the vendor of an 82559-based solution. the subsystem vendor id values are based upon the vendors pci vendor id and is controlled by the pci special interest group (sig). the subsystem id field identifies the 82559-based specific solution implemented by the vendor indicated in the subsystem vendor id field. the 82559 provides support for configurable subsystem vendor id and subsystem id fields. after hardware reset is de-asserted, the 82559 automatically reads addresses ah through ch of the eeprom. the first of these 16-bit values is used for controlling various 82559 functions. the second is the subsystem id value, and the third is the subsystem vendor id value. again, the default values for the subsystem id and subsystem vendor id are 0h and 0h, respectively. table 6. base address register functionalities register name pci function pci window cardbus function cardbus window bar0 memory csr 4 kbyte memory csr 4 kbyte bar1 i/o csr 4 kbyte i/o csr 4 kbyte bar2 flash 128 kbyte cis at offset + 64 kbyte 128 kbyte expansion bar a bootrom 1 mbyte n/a (disabled by eeprom) 1 mbyte a. the expansion bar can be disabled by setting the boot disable bit in the eeprom. bits r/w default description 31:4 r 1000h ethernet cis pointer (above the physical flash window) 3:0 r 3h cis in the flash window
82559 networking silicon 62 datasheet the 82559 checks bit numbers 15, 14, and 13 in the eeprom, word ah and functions according to table 7 below. the above table implies that if the 82559 detects the presence of an eeprom (as indicated by a value of 01b in bits 15 and 14), then bit number 13 determines whether the values read from the eeprom, words bh and ch, will be loaded into the subsystem id (word bh) and subsystem vendor id (word ch) fields. if bits 15 and 14 equal 01b and bit 13 equals 1b, the three least significant bits of the revision id field are programmed by bits 8-10 of the first eeprom word, word ah. between the de-assertion of reset and the completion of the automatic eeprom read, the 82559 does not respond to any pci configuration cycles. if the 82558 happens to be accessed during this time, it will retry the access. more information on retry is provided in section 4.2.1.1.3, retry premature accesses on page 20 . 8.1.13 capability pointer the capability pointer is a hard coded byte register with a value of dch. it provides an offset within the configuration space for the location of the power management registers. 8.1.14 interrupt line register the interrupt line register identifies which system interrupt request line on the interrupt controller the devices pci interrupt request pin (as defined in the interrupt pin register) is routed to. 8.1.15 interrupt pin register the interrupt pin register is read only and defines which of the four pci interrupt request pins, inta# through intd#, a pci device is connected to. the 82559 is connected the inta# pin. 8.1.16 minimum grant register the minimum grant (min_gnt) register is an optional read only register for bus masters and is not applicable to non-master devices. it defines the amount of time the bus master wants to retain pci bus ownership when it initiates a transaction. the default value of this register for the 82559 is 08h. table 7. 82559 id fields programming signature (bits 15:14) id (bit 13) altid (bit 7) device id vendor id revision id a subsystem id subsystem vendor id b-step c-step 11b b , 10b, 00b x x 1229h 8086h 08h 09h 0000h 0000h 01b 1b x 1229h 8086h word ah, bits 10:8 word ah, bits 10:8 word bh word ch 01b 0b 1b 1229h 8086h 08h 09h word bh word ch 01b 0b 0b 1029h 8086h 08h 09h word bh word ch a. the revision id is subject to change according to the silicon stepping. b. if bit 15 equals 1b, the eeprom is invalid and the default values are used.
networking silicon 82559 datasheet 63 8.1.17 maximum latency register the maximum latency (max_lat) register is an optional read only register for bus masters and is not applicable to non-master devices. this register defines how often a device needs to access the pci bus. the default value of this register for the 82559 is 18h. 8.1.18 capability id register the capability id is a byte register. it signifies whether the current item in the linked list is the register defined for pci power management. pci power management has been assigned the value of 02h. the 82559 is fully compliant with the pci power management specification, revision 2.2. 8.1.19 next item pointer the next item pointer is a byte register. it describes the location of the next item in the 82559s capability list. since power management is the last item in the list, this register is set to 0b. 8.1.20 power management capabilities register the power management capabilities register is a word read only register. it provides information on the capabilities of the 82559 related to power management. the 82559 reports a value of fe21h if it is connected to an auxiliary power source and 7e21h otherwise. it indicates that the 82559 supports wake-up in the d3 state if power is supplied, either v cc or v aux . table 8. power management capability register bits default read/write description 31:27 00011b (no v aux ) 11111b (v aux ) read only pme su pp ort. this five bit field indicates the power states in which the 82559 may assert pme#. the 82559 supports wake-up in all power states if it is fed by an auxiliary power supply (v aux ) and d0, d1, d2, and d3 hot if it is fed by pci power. 26 1b read only d2 su pp ort. if this bit is set, the 82559 supports the d2 power state. 25 1b read only d1 su pp ort. if this bit is set, the 82559 supports the d1 power state. 24:22 000b read only auxiliar y current. this field reports whether the 82559 implements the data registers. the auxiliary power consumption is the same as the current consumption reported in the d3 state in the data register. 21 1b read only device s p ecific initialization ( dsi ) . the dsi bit indicates whether special initialization of this function is required (beyond the standard pci configuration header) before the generic class device driver is able to use it. dsi is required for the 82559 after d3-to-d0 reset. 20 0b (pci) 1b (cardbus) read only reserved ( pci ) /auxiliar y power source ( cardbus ) . when this bit is set to 1, it indicates that the 82559 requires auxiliary power supplied by the system for wake-up from the d3 cold state. 19 0b read only pme clock. the 82559 does not require a clock to generate a power management event. 18:16 010b read only version. a value of 010b indicates that the 82559 complies with of the pci power management specification, revision 2.2.
82559 networking silicon 64 datasheet 8.1.21 power management control/status register (pmcsr) the power management control/status is a word register. it is used to determine and change the current power state of the 82559 and control the power management interrupts in a standard manner. 8.1.22 data register the data register is an 8-bit read only register that provides a mechanism for the 82559 to report state dependent maximum power consumption and heat dissipation. the value reported in this register depends on the value written to the data select field in the pmcsr register. the power measurements defined in this register have a dynamic range of 0 to 2.55 w with 0.01 w resolution according to the data scale. the value in this register is hard coded in the silicon. the structure of the data register differs between the 82559 b-step and c-step. the are presented below in table 10 and table 11 , respectively. table 9. power management control and status register bits default read/write description 15 0b read/clear pme status. this bit is set upon a wake-up event. it is independent of the state of the pme enable bit. if 1b is written to this bit, the bit will be cleared. it also de-asserts the pme# signal and clears the pme status bit in the power management driver register. when the pme# signal is enabled, the pme# signal reflects the state of the pme status bit. in a cardbus system, writing a 1b to this bit clears the gwake bit in the function event register. the function event register is described in section 9.1.14.1, lan function event register on page 77 . 14:13 00b read only data scale. this field indicates the data register scaling factor. it equals 10b for registers zero through eight and 00b for registers nine through fifteen. 12:9 0000b read only data select. this field is used to select which data is reported through the data register and data scale field. 8 0b read clear pme enable. this bit enables the 82559 to assert pme#. 7:5 000b read only reserved . these bits are reserved and should be set to 000b. 4 0b read only d y namic data. the 82559 does not support the ability to monitor the power consumption dynamically. 3:2 00b read only reserved. these bits are reserved and should be set to 00b. 1:0 00b read/write power state. this 2-bit field is used to determine the current power state of the 82559 and to set the 82559 into a new power state. the definition of the field values is as follows. 00 - d0 01 - d1 10 - d2 11 - d3 table 10. 82559 b-step ethernet data register data select data scale data reported 0 2 d0 power consumption = 58 (580 mw) 1 2 d1 power consumption = 40 (400 mw) 2 2 d2 power consumption = 40 (400 mw)
networking silicon 82559 datasheet 65 3 2 d3 power consumption = 40 (400 mw) 4 2 d0 power dissipated = 58 (580 mw) 5 2 d1 power dissipated = 40 (400 mw) 6 2 d2 power dissipated = 40 (400 mw) 7 2 d3 power dissipated = 40 (400 mw) 8 2 common function power dissipated = 00 9-15 0 reserved (00h) table 11. 82559 c-step ethernet data register data select data scale data reported 0 2 d0 power consumption = 60 (600 mw) 1 2 d1 power consumption = 42 (420 mw) 2 2 d2 power consumption = 42 (420 mw) 3 2 d3 power consumption = 42 (420 mw) 4 2 d0 power dissipated = 60 (600 mw) 5 2 d1 power dissipated = 42 (420 mw) 6 2 d2 power dissipated = 42 (420 mw) 7 2 d3 power dissipated = 42 (420 mw) 8 2 common function power dissipated = 00 9-15 0 reserved (00h) table 10. 82559 b-step ethernet data register data select data scale data reported
82559 networking silicon 66 datasheet 8.2 function 1: modem pci configuration space in pci systems and cardbus systems, the 82559 supports a dual function device: lan/modem. the lan is defined as function zero, and the modem is defined as function one. the modem function is active depending on the eeprom setup. the modem configuration registers define the resources required by the modem function. it is meaningful in a multifunction card design only. some of the modem configuration registers are a reflection of their matched ethernet registers. the registers values are pre-defined by hardware, initialized by the eeprom, or configurable through software. the shaded fields are described in detail in the following subsections. 8.2.1 modem configuration id register the modem configuration id field is a dword register composed of the device id and vendor id. it is a read only register and its value is loaded from the eeprom. modem configuration id 00h modem status modem command 04h modem revision id 08h bist modem header type latency timer cache line size 0ch modem i/o mapped base address register 10h modem memory mapped base address register 14h reserved base address register 18h reserved base address register 1ch reserved base address register 20h reserved base address register 24h reserved (pci)/modem cis pointer (cardbus) 28h modem subsystem id modem subsystem vendor id 2ch expansion rom base address register 30h reserved cap_ptr 34h reserved 38h max_lat min_gnt modem interrupt 3ch modem power management capabilities next item ptr capability id dch reserved modem data modem power management csr e0h figure 27. modem pci configuration registers
networking silicon 82559 datasheet 67 8.2.2 modem command register the modem command field is a 16 bit word register and provides basic control over the modems ability to respond to pci/cardbus accesses. the command registers structure is shown in the table below. 8.2.3 modem status register the modem status field is a 16 bit word register. it provides basic track of cardbus related events. all bits are cleared by pci rst#. table 12. power management control and status register bits default read/write description 15:10 000000b read only reserved. these bits are reserved and should be set to 000000b. 9 0b read only fast back-to-back. 8 0b read/write s y stem error enable. 7 0b read only wait c y cle enable. 6 0b read/write parit y error enable. 5 0b read only vga ( define ) . 4 0b read only memor y write and invalidate. 3 0b read only s p ecial c y cle. 2 0b read only master enable. 1 0b read/write memor y access enable. 0 0b read/write i/o access enable. table 13. modem status register bits default read/write description 15 0 read/write parit y error. 14 0 read/write s y stem error enable. 13:11 000 read only si g naled/received tar g et abort. 10:9 01 read only device select timin g . 8 0 read only data parit y detect. 7 0 read only fast back-to-back ca p able. 6:5 00 read only reserved. these bits are reserved and should be set to 00b. 4 1 read only new ca p abilit y . 3:0 0000 read only reserved. these bits are reserved and should be set to 0000b.
82559 networking silicon 68 datasheet 8.2.4 modem revision id register the modem revision id register is a dword, read only field. it is composed of the revision id byte and a 24-bit class code register. its value is loaded from the eeprom. the class code identifies the function as a modem. the class code and revision id are listed in the table below. 8.2.5 modem header type register the modem header type field is a byte wide, read only register. it indicates that this is a multifunction card and a value of 80h is hard coded in the silicon. 8.2.6 modem i/o base address register the modem i/o bar is a dword register that specifies the i/o base address for accessing the 82559s modem. the required i/o space is 8 bytes. 8.2.7 modem memory base address register the modem memory bar is a dword register that specifies the memory base address for accessing the 82559s modem port. the required memory space is 512 bytes. the memory space is used for both control registers and cis mapping. 8.2.8 modem cardbus cis pointer the cis pointer is a dword, hard coded, read only register. the cis pointer indicates whether or not the cis structure is located in the memory address space. the physical location of the cis structure is in the serial eeprom. the eeprom format is described in section 4.7, serial eeprom interface on page 33 . 8.2.9 modem subsystem vendor id register the modem subsystem vendor id is a 16 bit read only register. its value is loaded from the eeprom and is a reflection of register 2ch in function 0, lan (ethernet) function. table 14. modem revision register bits default read/write description 31:24 07h read only base class. this indicates that the 82559 is a communication device. 23:16 00h read only subclass. this indicates the serial controller equals 00h. 15:8 02h read only pro g ram interface. this indicates that the 82559 is 16550 uart compatible and initialized by eeprom word feh. 7:0 xxh read only revision number. this indicates the revision number and is initialized by eeprom word feh. bits r/w default description 31:4 r 0010h modem cis pointer (above the control registers) 3:0 r 2h cis in the memory base address register
networking silicon 82559 datasheet 69 8.2.10 modem subsystem id register the modem subsystem id is a 16 bit read only register. its value is loaded from the eeprom and is a reflection of register 2eh in function 0, lan (ethernet) function. 8.2.11 modem capabilities pointer the modem capability pointer is a hard coded, byte register that contains the value dch. it provides an offset within the configuration space for the location of the power management registers. 8.2.12 modem interrupt register the modem interrupt register specifies whether or not the modem requires an interrupt. this register is hard coded identically to register 3ch in function 0, lan (ethernet). it indicates that the modem requires interrupt support. note: the modem and ethernet functions share the same inta# pin. 8.2.13 modem power management capabilities register the modem power management capabilities register is a dword field that indicates if this function has power management capability, as well as identifying which power management capabilities are supported. the 82559 reports a value of fe31h if it is connected to an auxiliary power source and 7e21h otherwise. 8.2.14 modem power management control/status register the modem power management control/status register is a word register. it is used to manage the modems power management state. it also enables and monitors power management events. the modem power management control/status register structure is identical to register e0h in function 0, lan (ethernet) function. 8.2.15 modem data register the modem data register has similar functionality to register e2h in function 0, lan (ethernet). the register at location e2h reports power consumption of the modem function. the value of power consumption and power dissipation are loaded from the eeprom. table 15. ethernet data register data select data scale data reported 0 - 3 2 d0 to d3 power consumption (loaded from eeprom) 4 - 7 2 d0 to d3 power dissipated (loaded from eeprom) 8 - 15 0 reserved (00h)
82559 networking silicon 70 datasheet 8.2.16 modem support in pci mode the 82559 c-step supports modem interface in pci mode. the modem enable (mdm) bit in the eeprom can be activated in pci systems without the loss of bootrom support. in addition, bootrom support has been simplified. the 82559 c-step supports the co-existence of a bootrom flash device and a modem device (usin cfcs# with external glue logic). this is done by setting the mdm bit and clearing the boot disable (bd) bit in the eeprom. with this configuration, both the modem function and bootrom bar are active. the selection between the two functions is done through the boot enable bit (the least significant bit of bootrom bar in the lan pci configuration space). the 82559 will not support a lan/modem design if additional companion asics are operating on the flash/modem interface. this limitation does not affect companion asics that reside on the smb interface of the 82559.
networking silicon 82559 datasheet 71 9.0 control/status registers 9.1 lan (ethernet) control/status registers the 82559s control/status register (csr) is illustrated in the figure below. note: in figure 28 above, scb is defined as the system control block of the 82559, and pmdr is defined as the power management driver register. scb status word: the 82559 places the status of its command and receive units and interrupt indications in this register for the cpu to read. scb command word: the cpu places commands for the command and receive units in this register. interrupts are also acknowledged in this register. scb general pointer: the scb general pointer register points to various data structures in main memory depending on the current scb command word. port interface: the port interface allows the cpu to reset the 82559, force the 82559 to dump information to main memory, or perform an internal self test. flash control register: the flash control register allows the cpu to enable writes to an external flash. eeprom control register: the eeprom control register allows the cpu to read and write to an external eeprom. d31 upper word d16 d15 lower word d0 offset scb command word scb status word 00h system control block general pointer 04h port 08h eeprom control register flash control register 0ch management data interface (mdi) control register 10h receive direct memory access byte count 14h pmdr flow control register early receive int 18h reserved general status general control 1ch reserved 20h reserved 24h reserved 28h reserved 2ch function event register 30h function event mask register 34h function present state register 38h force event register 3ch figure 28. 82559 control/status register
82559 networking silicon 72 datasheet mdi control register: the mdi control register allows the cpu to read and write information from the phy unit (or an external phy component) through the management data interface. receive dma byte count: the receive dma byte count register keeps track of how many bytes of receive data have been passed into host memory via dma. flow control register: this register holds the flow control threshold value and indicates the flow control commands to the 82559. pmdr: the power management driver register provides an indication in memory and i/o space that a wake-up interrupt has occurred. the pmdr is described in further detail in section 9.1.11, power management driver register on page 75 . general control: the general control register allows the 82559 to enter the deep power-down state and provides the ability to disable the clockrun functionality. the general control register is described in further detail in section 9.1.12, general control register on page 76 . general status: the general status register describes the status of the 82559s duplex mode, speed, and link. the general status register is detailed in section 9.1.13, general status register on page 76 . function event: the function event register is used for cardbus power management applications and specifies the event that changed the status. the function event register is further defined in section 9.1.14.1, lan function event register on page 77 . function event mask: the function event mask register masks the cstschg signal assertion for specified events. the function event mask register is further defined in section 9.1.14.2, lan function event mask register on page 77 . function present state: the function present state register reflects the current state of each condition that may cause a status change or interrupt. the function present state register is further defined in section 9.1.14.3, lan function present state register on page 78 . force event: the force event register simulates the status change events for troubleshooting purposes. the force event register is further defined in section 9.1.14.4, lan force event register on page 79 .
networking silicon 82559 datasheet 73 9.1.1 system control block status word the system control block (scb) status word contains status information relating to the 82559s command and receive units. 9.1.2 system control block command word commands for the 82559s command and receive units are placed in this register by the cpu. bits name description 15 cx command unit ( cu ) executed. the cx bit indicates that the cu has completed executing a command with its interrupt bit set. 14 fr frame received. the fr bit indicates that the receive unit (ru) has finished receiving a frame. 13 cna cu not active. the cna bit is set when the cu is no longer active and in either an idle or suspended state. 12 rnr receive not read y . the rnr bit is set when the ru is not in the ready state. this may be caused by an ru abort command, a no resources situation, or set suspend bit due to a filled receive frame descriptor. 11 mdi mana g ement data interru p t. the mdi bit is set when a management data interface read or write cycle has completed. the management data interrupt is enabled through the interrupt enable bit (bit 29 in the management data interface control register in the csr). 10 swi software interru p t. the swi bit is set when software generates an interrupt. 9er earl y receive. the er bit is used for early receive interrupts. 8fcp flow control pause. the fcp bit is used as the flow control pause bit. 7:6 cus command unit status. the cus field contains the status of the command unit. 5:2 rus receive unit status. the rus field contains the status of the receive unit. 1:0 reserved these bits are reserved and should be set to 00b. bits name description 31:26 specific interrupt mask s p ecific interru p t mask. setting this bit to 1b causes the 82559 to stop generating an interrupt (in other words, de-assert the inta# signal) on the corresponding event. 25 si software generated interru p t. setting this bit to 1b causes the 82559 to generate an interrupt. writing a 0b to this bit has no effect. 24 m interru p t mask. if the interrupt mask bit is set to 1b, the 82559 will not assert its inta# pin. the m bit has higher precedence that the specific interrupt mask bits and the si bit. 23:20 cuc command unit command. this field contains the cu command. 19 reserved this bit is reserved and should be set to 0b. 18:16 ruc receive unit command. this field contains the ru command.
82559 networking silicon 74 datasheet 9.1.3 system control block general pointer the system control block (scb) general pointer is a 32-bit field that points to various data structures depending on the command in the cu command or ru command field. 9.1.4 port the port interface allows software to perform certain control functions on the 82559. this field is 32 bits wide: ? address and data (bits 32:4) ? port function selection (bits 3:0) the 82559 supports four port commands: software reset, self-test, selective reset, and dump. 9.1.5 flash control register the flash control register is a 32-bit field that allows access to an external flash device. 9.1.6 eeprom control register the eeprom control register is a 32-bit field that enables a read from and a write to the external eeprom. 9.1.7 management data interface control register the management data interface (mdi) control register is a 32-bit field and is used to read and write bits from the mdi. 9.1.8 receive direct memory access byte count the receive dma byte count register keeps track of how many bytes of receive data have been passed into host memory via dma. bits description 31:30 these bits are reserved and should be set to 00b. 29 interru p t enable. when this bit is set to 1b by software, the 82559 asserts an interrupt to indicate the end of an mdi cycle. 28 read y . this bit is set to 1b by the 82559 at the end of an mdi transaction. it should be reset to 0b by software at the same time the command is written. 27:26 o p code. these bits define the opcode: 01 for mdi write and 10 for mdi read. all other values (00 and 11) are reserved. 25:21 phy address. this field of bits contains the phy address. 20:16 phy re g ister address. this field of bits contains the phy register address. 15:0 data. in a write command, software places the data bits in this field, and the 82559 transfers the data to the phy unit. during a read command, the 82559 reads these bits serially from the phy unit, and software reads the data from this location.
networking silicon 82559 datasheet 75 9.1.9 early receive interrupt the early receive interrupt register allows the 82559 to generate an early interrupt depending on the length of the frame. an early interrupt is indicated by the er bit in the scb status word and the assertion of the inta# signal. 9.1.10 flow control register the flow control register contains the following fields: ? flow control command the flow control command field describes the action of the flow control process (for example, pause, on, or off). ? flow control threshold the flow control threshold field contains the threshold value (in other words, the number of free bytes in the receive fifo). 9.1.11 power management driver register the 82559 provides an indication in memory and i/o space that a wake-up event has occurred. it is located in the power management driver (pmdr). the pmdr is used for cardbus mode only. note: the pmdr is initialized at altrst# reset only. table 16. power management driver register bits default read/write description 31 0b read/clear link status chan g e indication. the link status change bit is set following a change in link status and is cleared by writing a 1b to it. 30 0b read/clear ma g ic packet. this bit is set when a magic packet is received regardless of the magic packet wake-up disable bit in the configuration command and the pme enable bit in the power management control/ status register. this bit is cleared by writing 1b to it. 29 0b read/clear interestin g packet. this bit is set when an interesting packet is received. interesting packets are defined by the 82559 packet filters. this bit is cleared by writing 1b to it. 28:26 000b read only reserved. these bits are reserved and should be set to 000b. 25 0b read/clear tco re q uest. this bit is set to 1b when the 82559 is busy with tco activity. 24 0b read/clear pme status. this bit is a reflection of the pme status bit in the power management control/status register (pmcsr). it is set upon a wake- up event and is independent of the pme enable bit. this bit is cleared by writing 1b to it. this also clears the pme status bit in the pmcsr and de-asserts the pme signal. in a cardbus system, if 1b is written to this field, the general wake-up (gwake) bit in the function event register is cleared.
82559 networking silicon 76 datasheet 9.1.12 general control register the general control register is a byte register and is described below. the general control register is used in cardbus mode only. 9.1.13 general status register the general status register is used in cardbus mode only and is a byte register which indicates the link status of the 82559. 9.1.14 ethernet card status change registers the pme signal used in pci systems is replaced by the card status change (cstschg) signal in cardbus systems. the cardbus specification requires the use of control/status registers related to cstschg. there are four event related registers. ? function event register : specifies the event that changed status ? function event mask register : masks cstschg signal assertion for specified events ? function present state register : reflects the current state of each condition that may cause a status change or interrupt ? force event register : simulates status change events for troubleshooting purposes these cardbus registers are used by software to determine which event has occurred, manage the event, and control the cstschg signal. table 17. general control register bits default read/write description 7:2 000000b read only reserved. these bits are reserved and should be set to 000000b. 1 0b read/write dee p power-down on link down enable. if a 1b is written to this field, the 82559 may enter a deep power-down state (sub-3 ma) in the d2 and d3 power states while the link is down. in this state, the 82559 does not keep link integrity. this state is not supported for point-to-point connection of two end stations. 0 0b read/write clockrun si g nal disable. if this bit is set to 1b, then the 82559 will always request the pci clock signal. this mode can be used to overcome potential receive overruns caused by clockrun signal latencies over 5 m s. table 18. general status register bits default read/write description 7:3 00000b read only reserved. these bits are reserved and should be set to 00000b. 2 -- read only du p lex mode. this bit indicates the wire duplex mode: full duplex (1b) or half duplex (0b). 1 -- read only s p eed. this bit indicates the wire speed: 100 mbps (1b) or 10 mbps (0b). 0 0b read only link status indication. this bit indicates the status of the link: valid (1b) or invalid (0b).
networking silicon 82559 datasheet 77 the 82559 supports only the interrupt and general wake-up event bits in the card status change registers. these registers compliment the pci power management registers in a non-acpi compliant os. they are initialized by a power-up reset on the altrst# pin. the location of these registers should be specified within the configuration space pointing to offset address 30h of the csr. note: access to the cstschg registers in pci mode is forbidden. 9.1.14.1 lan function event register the function event register specified the event that changed the status. 9.1.14.2 lan function event mask register the function event mask register masks cstschg and inta# assertion. table 19. lan function event register bits function default description 31:16 reserved 0 bits [31:16] are reserved in the cardbus specification. 15 intr 0b this bit is used for as the interrupt bit. it is set when the ethernet interrupt source is set, regardless of the mask value. it is cleared when the os writes 1b to this field and the interrupt source has been serviced. writing 0b to this field has no effect. 14:5 reserved 0 bits [14:5] are reserved in the cardbus specification. 4gwake0b this bit is used for general wake-up. it is set when the ethernet wake- up source is set, regardless of the mask value. writing 1b to this field clears this bit and the pme status bit in the pmcsr. writing 0b to this field has no effect. note that writing 1b to the pme status bit in the pmcsr has the same effect. 3 reserved 0b bit 3 is reserved in the cardbus specification. 2 bvd rdy 0b bit 2 is used as the battery voltage detect ready (bvd rdy) bit. 1 bvd wp 0b bit 1 is used as the bvd write protect (wp) bit. 0 reserved 0b bit 0 is reserved in the cardbus specification. table 20. lan function event mask register bits function default description 31:16 reserved 0 bits [31:16] are reserved in the cardbus specification. 15 intr 0b this bit is the interrupt mask. when this bit equals 0b, it masks the ethernet function inta# line but has no effect on the lan function event register. the ethernet function can assert the inta# signal only when both fields are enabled: the interrupt bit and the m bit in the system control block (scb) register within the csr space. the interrupt mask bit affects the inta# masking. 14 wkup 0b this bit is the wake-up mask. when this bit equals 0b, it masks the ethernet function cstschg signal but has no effect on the lan function event register. this bit is dependent on bit 4 of this register. 13:7 reserved 0 bits [13:7] are reserved in the cardbus specification. 6:5 pwm bam 0 these bits are used for pulse width modulation binary audio enable (pwm bam).
82559 networking silicon 78 datasheet 9.1.14.3 lan function present state register the function present state register reflects the current state of the lan function that may cause a status change or interrupt. 4 gwake 0b this bit is the general wake-up mask. when this bit equals 0b, it masks the ethernet function wake-up events towards the cstschg signal. it has no effect on the lan function event register. the 82559 can assert the cstschg signal in the following configuration of masked bits: wake-up bit and general wake-up bit, or pme enable bit in the pmcsr register only. 3 reserved 0b bit 3 is reserved in the cardbus specification. 2 bvd rdy 0b bit 2 is used as the battery voltage detect ready (bvd rdy) bit. 1 bvd wp 0b bit 1 is used as the bvd write protect (wp) bit. 0 reserved 0b bit 0 is reserved in the cardbus specification. table 20. lan function event mask register bits function default description table 21. lan function present state register bits function default description 31:16 reserved 0 bits [31:16] are reserved in the cardbus specification. 15 intr 0 this bit is used for interrupts. it reflects the current state of the ethernet source of the interrupt regardless of the mask value. it is set when the ethernet function has a pending interrupt and cleared when the software driver acknowledges all active interrupts through the scb command word. 14:5 reserved 0 bits [14:5] are reserved in the cardbus specification. 4 gwake 0 this bit is used for general wake-up. it reflects the current state of the ethernet source of cstschg. it is a logical or result of the gated three most significant bits in the pmdr: link status change, magic packet, and interesting packet. the link status change bit is gated by the link status change wake enable bit in the configuration command. the magic packet bit is gated by the magic packet wake-up disable bit in the configuration command. the interesting packet bit is gated by the programmable filter command. 3 reserved 0b bit 3 is reserved in the cardbus specification. 2 bvd rdy 0b bit 2 is used as the battery voltage detect ready (bvd rdy) bit. 1 bvd wp 0b bit 1 is used as the bvd write protect (wp) bit. 0 reserved 0b bit 0 is reserved in the cardbus specification.
networking silicon 82559 datasheet 79 9.1.14.4 lan force event register the force event register simulates status change events for troubleshooting purposes. this register provides the ability to simulate events by forcing values into the function event register. 9.2 statistical counters the 82559 provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. the counters are updated by the 82559 when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). the statistical counters are reported to the software on demand by issuing the dump statistical counters command or dump and reset statistical counters command in the scb command unit command (cuc) field. table 22. lan force event register bits function default description 31:16 reserved 0 bits [31:16] are reserved in the cardbus specification. 15 intr 0 this bit is used for interrupts. writing 1b in this field will set the interrupt bit in the lan function event register. if the inta# pin is not masked, then it will also be activated. writing 0b has no effect. 14:5 reserved 0 bits [14:5] are reserved in the cardbus specification. 4gwake0 this bit is used for general wake-up. writing 1b in this field will set the cstschg bit in the lan function event register. if the cstschg pin is not masked, then it will also be activated. writing 0b has no effect. 3:0 reserved 0 bits [3:0] are reserved in the cardbus specification. table 23. 82558 statistical counters id counter description 0 transmit good frames this counter contains the number of frames that were transmitted properly on the link. it is updated only after the actual transmission on the link is completed, not when the frame was read from memory as is done for the transmit command block status. 4 transmit maximum collisions (maxcol) errors this counter contains the number of frames that were not transmitted because they encountered the configured maximum number of collisions. 8 transmit late collisions (latecol) errors this counter contains the number of frames that were not transmitted since they encountered a collision later than the configured slot time. 12 transmit underrun errors a transmit underrun occurs because the system bus cannot keep up with the transmission. this counter contains the number of frames that were either not transmitted or retransmitted due to a transmit dma underrun. if the 82559 is configured to retransmit on underrun, this counter may be updated multiple times for a single frame. 16 transmit lost carrier sense (crs) this counter contains the number of frames that were transmitted by the 82559 despite the fact that it detected the de-assertion of crs during the transmission. 20 transmit deferred this counter contains the number of frames that were deferred before transmission due to activity on the link.
82559 networking silicon 80 datasheet 24 transmit single collisions this counter contains the number of transmitted frames that encountered one collision. 28 transmit multiple collisions this counter contains the number of transmitted frames that encountered more than one collision. 32 transmit total collisions this counter contains the total number of collisions that were encountered while attempting to transmit. this count includes late collisions and frames that encountered maxcol. 36 receive good frames this counter contains the number of frames that were received properly from the link. it is updated only after the actual reception from the link is completed and all the data bytes are stored in memory. 40 receive crc errors this counter contains the number of aligned frames discarded because of a crc error. this counter is updated, if needed, regardless of the receive unit state. the receive crc errors counter is mutually exclusive of the receive alignment errors and receive short frame errors counters. 44 receive alignment errors this counter contains the number of frames that are both misaligned (for example, crs de-asserts on a non-octal boundary) and contain a crc error. the counter is updated, if needed, regardless of the receive unit state. the receive alignment errors counter is mutually exclusive of the receive crc errors and receive short frame errors counters. 48 receive resource errors this counter contains the number of good frames discarded due to unavailability of resources. frames intended for a host whose receive unit is in the no resources state fall into this category. if the 82559 is configured to save bad frames and the status of the received frame indicates that it is a bad frame, the receive resource errors counter is not updated. 52 receive overrun errors this counter contains the number of frames known to be lost because the local system bus was not available. if the traffic problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted. 56 receive collision detect (cdt) this counter contains the number of frames that encountered collisions during frame reception. 60 receive short frame errors this counter contains the number of received frames that are shorter than the minimum frame length. the receive short frame errors counter is mutually exclusive to the receive alignment errors and receive crc errors counters. a short frame will always increment only the receive short frame errors counter. 64 flow control transmit pause this counter contains the number of flow control frames transmitted by the 82559. this count includes both the xoff frames transmitted and xon (pause(0)) frames transmitted. 68 flow control receive pause this counter contains the number of flow control frames received by the 82559. this count includes both the xoff frames received and xon (pause(0)) frames received. table 23. 82558 statistical counters id counter description
networking silicon 82559 datasheet 81 the statistical counters are initially set to zero by the 82559 after reset. they cannot be preset to anything other than zero. the 82559 increments the counters by internally reading them, incrementing them and writing them back. this process is invisible to the cpu and pci bus. in addition, the counters adhere to the following rules: ? the counters are wrap-around counters. after reaching ffffffffh the counters wrap around to 0. ? the 82559 updates the required counters for each frame. it is possible for more than one counter to be updated as multiple errors can occur in a single frame. ? the counters are 32 bits wide and their behavior is fully compatible with the ieee 802.1 standard. the 82559 supports all mandatory and recommend statistics functions through the status of the receive header and directly through these statistical counters. the cpu can access the counters by issuing a dump statistical counters scb command. this provides a snapshot, in main memory, of the internal 82559 statistical counters. the 82559 supports 21 counters. the dump could consist of the either 16, 19, or all 21 counters, depending on the status of the extended statistics counters and tco statistics configuration bits in the configuration command (described in the 82559 software developers manual ). 9.3 modem control/status registers access to modem based memory or i/o ports are mapped to a cycle to the modem with the lowest 16 addresses of the pci address space mapped to the address bus of the modem, which is connected to fla[3:0]. 9.3.1 modem base memory addressing the modem base memory addressing is an 8-byte address space. there are three types of address spaces: ? modem chipset address space: 0h to fh ? modem function address space: 80h to ffh (implemented in 82559) 72 flow control receive unsupported this counter contains the number of mac control frames received by the 82559 that are not flow control pause frames. these frames are valid mac control frames that have the predefined mac control type value and a valid address but has an unsupported opcode. 76 receive tco frames this counter contains the number of tco packets received by the 82559. 78 transmit tco frames this counter contains the number of tco packets transmitted. table 23. 82558 statistical counters id counter description
82559 networking silicon 82 datasheet ? modem cis address space: 100h to 1ffh (loaded from eeprom) 9.3.2 modem base i/o addressing the modem base i/o addressing is an 8-byte address space. during i/o cycles, accesses to the modem port are byte accesses. fla3 is kept low while fla[2:0] are mapped according to the pci byte address offset. 9.3.3 modem cardbus cstchg registers the modem cardbus cstchg registers are used in cardbus mode only. there are four event related registers. the cardbus software uses the registers to determine which event has occurred and manage the event and to control the cstschg signal. the 82559 supports only the interrupt and general wake-up event bits in the cstschg registers. these registers compliment the pci power management registers for the use with non-acpi compliant os. it is initialized by power-up reset driven on the altrst# pin. 9.3.3.1 modem function event register the modem function event register specifies the event that changed its status. it is identical to the ethernet function event register described in section 9.1.14.1, lan function event register on page 77 . byte offset register description 0h:7h modem controller mimic port, isa address space 0:7 0h:3fh modem chipset address space (external modem ports) 8h:fh modem controller resource management port (rmp), isa address space 8:15 10h:3fh general purpose address space 80h:83h modem control register: reset[0], central site mode[1] e0h:e3h reserved f0h:f3h modem function event register f4h:f7h modem function mask register f8h:fbh modem function present register fch:ffh modem force function event register 100h:1ffh cis area (loaded from the eeprom) byte offset register description 0h:7h venus mimic port, isa address space 0:7
networking silicon 82559 datasheet 83 9.3.3.2 modem function event mask register the modem function event mask register masks cstschg and inta# assertion as shown in table 24 below. 9.3.3.3 modem function present state register the modem function present state register specifies the current state of an events sources as shown in table 25 below. table 24. modem function event mask register bits function default description 31:16 reserved 0 bits [31:16] are reserved in the cardbus specification. 15 intr 0b this bit is the interrupt mask. when this bit equals 0b, it masks the modem function inta# line but has no effect on the modem function event register. the modem function can assert the inta# signal only when both fields are enabled: the interrupt bit and the modem control bit in the system control block (scb) register within the csr space. the interrupt mask bit affects the inta# masking only after the os has set this register. thus, on legacy systems that do not access the status change registers, the modem inta# signal is not masked by the interrupt. 14 wkup 0b this bit is the wake-up mask. when this bit equals 0b, it masks the modem function cstschg signal but has no effect on the function event register. this bit is dependent on bit 4 of this register. 13:7 reserved 0 bits [13:7] are reserved in the cardbus specification. 6:5 pwm bam 0 these bits are used for pulse width modulation binary audio enable. (pwm bam). 4gwake0b this bit is the general wake-up mask. when this bit equals 0b, it masks the modem function wake-up events towards the cstschg signal. it has no effect on the modem function event register. the 82559 can assert the cstschg signal in the following configuration of masked bits: wake-up bit and general wake-up bit, or pme enable bit in the pmcsr register only. 3 reserved 0b bit 3 is reserved in the cardbus specification. 2 bvd rdy 0b bit 2 is used as the battery voltage detect ready (bvd rdy) bit. 1 bvd wp 0b bit 1 is used as the bvd write protect (wp) bit. 0 reserved 0b bit 0 is reserved in the cardbus specification. table 25. modem function present state register bits function default description 31:16 reserved 0 bits [31:16] are reserved in the cardbus specification. 15 intr 0 this bit is used for interrupts. it reflects the current state of the modem interrupt (mint) input pin from the modem. 14:5 reserved 0 bits [14:5] are reserved in the cardbus specification. 4gwake0 this bit is used for general wake-up. it reflects the current inverse state of the modem ring (mring#) input pin from the modem. 3 reserved 0b bit 3 is reserved in the cardbus specification.
82559 networking silicon 84 datasheet 9.3.3.4 modem force event register the modem force event register simulates status change events for troubleshooting purposes. it is identical to the ethernet force event register described in section 9.1.14.4, lan force event register on page 79 . 2 bvd rdy 0b bit 2 is used as the batter voltage detect (bvd rdy) bit. 1 bvd wp 0b bit 1 is used as the bvd write protect (wp) bit. 0 reserved 0b bit 0 is reserved in the cardbus specification. table 25. modem function present state register bits function default description
networking silicon 82559 datasheet 85 10.0 phy unit registers the 82559 provides status and accepts management information via the management data interface (mdi) within the csr space. acronyms mentioned in the registers are defined as follows: sc: self cleared. ro: read only. e: eeprom setting affects content. ll: latch low. lh: latch high. 10.1 mdi registers 0 - 7 10.1.1 register 0: control register bit definitions bit(s) name description default r/w 15 reset this bit sets the status and control register of the phy to their default states and is self-clearing. the phy returns a value of one until the reset process has completed and accepts a read or write transaction. 1 = phy reset 0rw sc 14 loopback this bit enables loopback of transmit data nibbles from the txd[3:0] signals to the receive data path. the phy units receive circuitry is isolated from the network. note that this may cause the descrambler to lose synchronization and produce 560 nanoseconds of dead time. note also that the loopback configuration bit takes priority over the loopback mdi bit. 1 = loopback enabled 0 = loopback disabled (normal operation) 0rw 13 speed selection this bit controls speed when auto-negotiation is disabled and is valid on read when auto-negotiation is disabled. 1 = 100 mbps 0 = 10 mbps 1rw 12 auto-negotiation enable this bit enables auto-negotiation. bits 13 and 8, speed selection and duplex mode, respectively, are ignored when auto-negotiation is enabled. 1 = auto-negotiation enabled 0 = auto-negotiation disabled 1rw 11 power-down this bit sets the phy unit into a low power mode. in low power mode, the phy unit consumes no more than 30 ma. 1 = power-down enabled 0 = power-down disabled (normal operation) 0rw 10 reserved this bit is reserved and should be set to 0b. 0 rw
82559 networking silicon 86 datasheet 10.1.2 register 1: status register bit definitions 9 restart auto- negotiation this bit restarts the auto-negotiation process and is self- clearing. 1 = restart auto-negotiation process 0rw sc 8 duplex mode this bit controls the duplex mode when auto-negotiation is disabled. if the phy reports that it is only able to operate in one duplex mode, the value of this bit shall correspond to the mode which the phy can operate. when the phy is placed in loopback mode, the behavior of the phy shall not be affected by the status of this bit, bit 8. 1 = full duplex 0 = half duplex 0rw 7 collision test this bit will force a collision in response to the assertion of the transmit enable signal. 1 = force col 0 = do not force col 0rw 6:0 reserved these bits are reserved and should be set to 0000000b. 0 rw bit(s) name description default r/w 15 reserved this bit is reserved and should be set to 0b. 0 ro e 14 100base-tx full duplex 1 = phy able to perform full duplex 100base-tx 1 ro 13 100 mbps half duplex 1 = phy able to perform half duplex 100base-tx 1 ro 12 10 mbps full duplex 1 = phy able to operate at 10mbps in full duplex mode 1ro 11 10 mbps half duplex 1 = phy able to operate at 10 mbps in half duplex mode 1ro 10:7 reserved these bits are reserved and should be set to 0000b. 0 ro 6 management frames preamble suppression 0 = phy will not accept management frames with preamble suppressed 0ro 5 auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process has not completed 0ro 4 remote fault 0 = no remote fault condition detected 0 ro 3 auto-negotiation ability 1 = phy is able to perform auto-negotiation 1 ro 2 link status 1 = valid link has been established 0 = invalid link detected 0ro ll 1 jabber detect 1 = jabber condition detected 0 = no jabber condition detected 0ro lh 0 extended capability 1 = extended register capabilities enabled 1 ro bit(s) name description default r/w
networking silicon 82559 datasheet 87 10.1.3 register 2: phy identifier register bit definitions 10.1.4 register 3: phy identifier register bit definitions 10.1.5 register 4: auto-negotiation advertisement register bit definitions 10.1.6 register 5: auto-negotiation link partner ability register bit definitions bit(s) name description default r/w 15:0 phy id (high byte) value: 02a8h -- ro bit(s) name description default r/w 15:0 phy id (low byte) value: 0154h -- ro bit(s) name description default r/w 15 next page constant 0 = transmitting primary capability data page 0ro 14 reserved this bit is reserved and should be set to 0b. 0 ro 13 remote fault 1 = indicate link partners remote fault 0 = no remote fault 0rw 12:5 technology ability field technology ability field is an 8-bit field containing information indicating supported technologies specific to the selector field value. 00101111 rw 4:0 selector field the selector field is a 5-bit field identifying the type of message to be sent via auto-negotiation. this field is read only in the 82559 and contains a value of 00001b, ieee standard 802.3. 00001 ro bit(s) name description default r/w 15 next page this bit reflects the phys link partners auto- negotiation ability. -- ro 14 acknowledge this bit is used to indicate that the 82559s phy unit has successfully received its link partners auto- negotiation advertising ability. -- ro 13 remote fault this bit reflects the phys link partners auto- negotiation ability. -- ro 12:5 technology ability field this bit reflects the phys link partners auto- negotiation ability. -- ro 4:0 selector field this bit reflects the phys link partners auto- negotiation ability. -- ro
82559 networking silicon 88 datasheet 10.1.7 register 6: auto-negotiation expansion register bit definitions 10.2 mdi registers 8 - 15 registers eight through fifteen are reserved for ieee. 10.3 mdi register 16 - 31 10.3.1 register 16: phy unit status and control register bit definitions bit(s) name description default r/w 15:5 reserved these bits are reserved and should be set to 0b. 0 ro 4 parallel detection fault 1 = fault detected via parallel detection (multiple link fault occurred) 0 = no fault detected via parallel detection this bit will self-clear on read 0ro sc lh 3 link partner next page able 1 = link partner is next page able 0 = link partner is not next page able 0ro 2 next page able 1 = local drive is next page able 0 = local drive is not next page able 0ro 1 page received 1 = new page received 0 = new page not received this bit will self-clear on read. 0ro sc lh 0 link partner auto- negotiation able 1 = link partner is auto-negotiation able 0 = link partner is not auto-negotiation able 0ro bit(s) name description default r/w 15:14 reserved these bits are reserved and should be set to 00b 00 rw 13 carrier sense disconnect control this bit enables the disconnect function. 1 = disconnect function enabled 0 = disconnect function disabled 0rw 12 transmit flow control disable this bit enables transmit flow control 1 = transmit flow control enabled 0 = transmit flow control disabled 0rw 11 receive de- serializer in-sync indication this bit indicates status of the 100base-tx receive de-serializer in-sync. -- ro 10 100base-tx power-down this bit indicates the power state of 100base-tx phy unit. 1 = power-down 0 = normal operation 1ro
networking silicon 82559 datasheet 89 10.3.2 register 17: phy unit special control bit definitions 9 10base-t power-down this bit indicates the power state of 100base-tx phy unit. 1 = power-down 0 = normal operation 1ro 8 polarity this bit indicates 10base-t polarity. 1 = reverse polarity 0 = normal polarity -- ro 7:2 reserved these bits are reserved and should be set to 0b. 000000 ro 1 speed this bit indicates the auto-negotiation result. 1 = 100 mbps 0 = 10 mbps -- ro 0 duplex mode this bit indicates the auto-negotiation result. 1 = full duplex 0 = half duplex -- ro bit(s) name description default r/w 15 scrambler by- pass 1 = by-pass scrambler 0 = normal operations 0rw 14 by-pass 4b/5b 1 = 4 bit to 5 bit by-pass 0 = normal operation 0rw 13 force transmit h- pattern 1 = force transmit h-pattern 0 = normal operation 0rw 12 force 34 transmit pattern 1 = force 34 transmit pattern 0 = normal operation 0rw 11 good link 1 = 100base-tx link good 0 = normal operation 0rw 10 reserved this bit is reserved and should be set to 0b. 0 rw 9 transmit carrier sense disable 1 = transmit carrier sense disabled 0 = transmit carrier sense enabled 0rw 8 disable dynamic power-down 1 = dynamic power-down disabled 0 = dynamic power-down enabled (normal) 0rw 7 auto-negotiation loopback 1 = auto-negotiation loopback 0 = auto-negotiation normal mode 0rw 6 mdi tri-state 1 = mdi tri-state (transmit driver tri-states) 0 = normal operation 0rw 5 filter by-pass 1 = by-pass filter 0 = normal filter operation 0rw 4 auto polarity disable 1 = auto polarity disabled 0 = normal polarity operation 0rw 3 squelch disable 1 = 10base-t squelch test disable 0 = normal squelch operation 0rw bit(s) name description default r/w
82559 networking silicon 90 datasheet 10.3.3 register 18: phy address register 10.3.4 register 19: 100base-tx receive false carrier counter bit definitions 10.3.5 register 20: 100base-tx receive disconnect counter bit definitions 10.3.6 register 21: 100base-tx receive error frame counter bit definitions 2 extended squelch 1 = 10base-t extended squelch control enabled 0 = 10base-t extended squelch control disabled 0rw 1 link integrity disable 1 = link disabled 0 = normal link integrity operation 0rw 0 jabber function disable 1 = jabber disabled 0 = normal jabber operation 0rw bit(s) name description default r/w 15:5 reserved these bits are reserved and should be set to a constant 0 0ro 4:0 phy address these bits are set to the phys address, 00001b. 1 ro bit(s) name description default r/w 15:0 receive false carrier these bits are used for the false carrier counter. -- ro sc bit(s) name description default r/w 15:0 disconnect event this field contains a 16-bit counter that increments for each disconnect event. the counter freezes when full and self-clears on read -- ro sc bit(s) name description default r/w 15:0 receive error frame this field contains a 16-bit counter that increments once per frame for any receive error condition (such as a symbol error or premature end of frame) in that frame. the counter freezes when full and self-clears on read. -- ro sc bit(s) name description default r/w
networking silicon 82559 datasheet 91 10.3.7 register 22: receive symbol error counter bit definitions 10.3.8 register 23: 100base-tx receive premature end of frame error counter bit definitions 10.3.9 register 24: 10base-t receive end of frame error counter bit definitions 10.3.10 register 25: 10base-t transmit jabber detect counter bit definitions 10.3.11 register 26: equalizer control and status bit definitions bit(s) name description default r/w 15:0 symbol error counter this field contains a 16-bit counter that increments for each symbol error. the counter freezes when full and self-clears on read. in a frame with a bad symbol, each sequential six bad symbols count as one. -- ro sc bit(s) name description default r/w 15:0 premature end of frame this field contains a 16-bit counter that increments for each premature end of frame event. the counter freezes when full and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 end of frame counter this is a 16-bit counter that increments for each end of frame error event. the counter freezes when full and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 jabber detect counter this is a 16-bit counter that increments for each jabber detection event. the counter freezes when full and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 rfu reserved for future use -- rw
82559 networking silicon 92 datasheet 10.3.12 register 27: phy unit special control bit definitions bit(s) name description default r/w 15:3 reserved these bits are reserved and should be set to 0b. 0 rw 2:0 led switch control value 000 001 010 011 100 101 110 111 actled activity speed speed activity off off on on liled link collision link collision off on off on 000 rw
networking silicon 82559 datasheet 93 11.0 82559 test port functionality 11.1 introduction the 82559s nand tree test access port (tap) is the access point for test data to and from the device. the port provides the ability to perform basic production level testing. the port provides two functions: ? the synchronous ic validation mode is used in the production of the device. this mode gives the signals their names (for example, testability port clock [tck]). ? the 82559 also supports asynchronous testing modes. these test modes support the validation of connections at the board level. 11.2 asynchronous test mode four asynchronous test modes are supported for system level design use. the modes are selected through the use of the test port input pin in static combinations. the test port pins are test port (test), test port data input (ti), test port execute enable (texec) and test port clock (tck). during normal operation the test pin must be pulled down through a resistor (pulling test high enables the test mode). all other port inputs may have a pull-down at the designers discretion. 11.3 test function description the 82559 tap mode supports several tests that can be used in board level design. these tests help verify basic functionality as well as test the integrity of solder connection on the board. the tests are described in the following subsections. 11.3.1 tristate the tristate command sets all 82559 input and output pins into a tristate (high-z) mode (all internal pull-ups and pull-downs are disabled). this mode is entered by setting the following test pin combination and resetting the device: test = 1 texec = 0 tck = 0 ti = 1 11.3.2 nand tree the nand tree test mode is the most useful of the asynchronous test modes. it enables the placement of the 82559 to be validated at board test. the nand tree was chosen for its speed advantages. modern automated test equipment can perform a complete peripheral scan without support at the board level. this command connects all outputs of the input buffers in the device periphery into a nand tree scheme. all the output drivers of the output buffers, except the test port data output (to) pin, are put into high-z mode. these pins are driven to affect the output of the tree. there are two separate chains and associated outputs for speed. any hard strapped pins will prevent the tester from scanning correctly. this mode is entered by placing the test pins in the following combination:
82559 networking silicon 94 datasheet test = 1 texec = 1 tck = 0 ti = 1 there are two nand tree chains with two separate outputs assigned to floe# (chain 1) and flwe# (chain 2). table 26. nand tree chains chain order (nand tree output) chain 1 (floe#) chain 2 (flwe#) 1 rst# liled 2 idsel actled# 3 req# speedled 4 ad23 smbalrt# 5 serr# smbclk 6 ad22 smbd 7 ad21 isolate# 8 ad20 altrst# 9 ad19 clkrun# 10 ad18 ad31 11 ad17 ad30 12 c/be2# ad29 13 frame# ad28 14 irdy# ad27 15 trdy# pme# 16 clk cstschg 17 devsel# ad26 18 inta# ad25 19 stop# c/be3# 20 gnt# ad24 21 perr# fld0 22 par fld1 23 ad16 fld2 24 c/be1# fld3 25 ad15 fld4 26 ad14 fld5 27 ad13 fld6 28 ad12 fld7 29 ad11 fla0 30 ad10 fla1 31 ad9 fla2 32 ad8 fla3 33 c/be0# fla4
networking silicon 82559 datasheet 95 34 ad7 fla5 35 ad6 fla6 36 ad5 fla7 37 ad4 fla8 37 ad3 fla9 39 ad2 fla10 40 ad1 fla11 41 ad0 fla12 42 eecs fla13/eedi 43 fla14/eedo 44 fla15/eesk 45 fla16 46 flcs# 47 cfclk 48 cfcs# table 26. nand tree chains chain order (nand tree output) chain 1 (floe#) chain 2 (flwe#)
82559 networking silicon 96 datasheet
networking silicon 82559 datasheet 97 12.0 electrical and timing specifications 12.1 absolute maximum ratings maximum ratings are listed below: case temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 c to 85 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to 140 c outputs and supply voltages (except pci and smb) . . . . . . . . . . . . . . . . . . . . . -0.5 v to 5.0 v pci and smb output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 v to 5.25 v transmit data output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v to 8.0 v input voltages (except pci and smb). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 v to 5.0 v pci and smb input voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 v 6.0 v stresses above the listed absolute maximum ratings may cause permanent damage to the 82559 device. this is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 12.2 dc specifications notes: 1. v io should be 5 v 5% in any pci environment (either 5 v or 3.3 v signaling). in cardbus, v io must be identical to v cc . 2. typical current consumption is in nominal operating conditions (v cc = 3.3 v) and average link activity. maximum current consumption is in maximum v cc and maximum link activity. the 82559 supports both the pci and cardbus interface standards. in the pci mode, the 82559 is five volts tolerant and supports both 5 v and 3.3 v signaling environments. table 27. general dc specifications symbol parameter condition min typical max units notes v cc supply voltage 3.0 3.3 3.5 v v io periphery clamp voltage pci 4.75 5.0 5.25 v 1 cardbus 3.0 3.3 3.6 v 1 i cc power supply 125 195 ma 2 table 28. pci/cardbus interface dc specifications symbol parameter condition min max units notes v ihp input high voltage 0.475v cc v io + 0.5 v v ilp input low voltage -0.5 0.325v cc v v ipup input pull-up voltage 0.7v cc v1 v ipdp input pull-down voltage 0.2v cc v1 i ilp input leakage current 0 < v in < v cc 10 m a2
82559 networking silicon 98 datasheet notes: 1. these values are only applicable in 3.3 v signaling environments (pci or cardbus). outside of this limit the input buffer must consume its minimum current. 2. input leakage currents include high-z output leakage for all bidirectional buffers with tristate outputs. 3. signals without pull-up resistors have 3 ma low output current; and signals requiring pull-up resistors, 6 ma. the signals requiring pull-up resistors include: frame#, trdy#, irdy#, devsel#, stop#, serr# and perr#. 4. this value is characterized but not tested. note: smb outputs (smbalrt#, smbd, and smbclk) are open drain. note: 1. this value is characterized but not tested. v ohp output high voltage i out = -2 ma i out = -500 m a i out = -150 m a 2.4 0.9v cc 0.9v cc v v v pci cardbus v olp output low voltage i out = 3 ma, 6 ma i out = 1500 m a i out = 700 m a 0.55 0.1v cc 0.1v cc v v v 3, pci cardbus c inp input pin capacitance 10 pf 4 c clkp clk pin capacitance 5 12 pf 4 c idsel idsel pin capacitance 8 pf 4 l pinp pin inductance 12 nh 4 table 28. pci/cardbus interface dc specifications table 29. smb interface dc specifications symbol parameter condition min max units notes v ihs input high voltage 1.4 v io + 0.5 v v ils input low voltage -0.5 0.6 v i ils input low leakage current 0 < v in < v cc 1.0 m a v ols output low voltage i pullup = 100 m a 0.4 v table 30. flash/modem/eeprom interface dc specifications symbol parameter condition min max units notes v ihl input high voltage 2.0 v cc + 0.5 v v ill input low voltage -0.5 0.8 v i ill input low leakage current 0 < v in < v cc 20 m a v ohl output high voltage i out = -1 ma 2.4 v v oll output low voltage i out = 2ma 0.4 v c inl input pin capacitance 10 pf 1
networking silicon 82559 datasheet 99 notes: 1. current is measured on all v cc pins (v cc = 3.3 v). 2. transmitter peak current is attained by dividing the measured maximum differential output peak voltage by the load resistance value. table 31. led voltage/current characteristics symbol parameter condition min typical max units notes v ohled output high voltage i out = -10 ma 2.4 v v olled output low voltage i out = 10 ma 0.7 v table 32. 100base-tx voltage/current characteristics symbol parameter condition min typical max units notes r id100 input differential impedance dc 10 k w v ida100 input differential accept peak voltage 500 0.7 mv v idr100 input differential reject peak voltage 100 mv v icm100 input common mode voltage v cc /2 v v od100 output differential peak voltage 0.95 1.00 1.05 v i cct100 line driver supply peak current rbias100 = 619 w 20 ma 1 figure 29. rbias100 resistance versus transmitter current rbias100 585 0hm 619 ohm 650 ohm icct100 19ma 20 ma 21ma
82559 networking silicon 100 datasheet notes: 1. current is measured on all v cc pins (v cc = 3.3 v). 2. transmitter peak current is attained by dividing the measured maximum differential output peak voltage by the load resistance value. table 33. 10base-t voltage/current characteristics symbol parameter condition min typical max units notes r id10 input differential impedance 10 mhz 10 k w v ida10 input differential accept peak voltage 5 mhz f 10 mhz 585 440 3100 mv v idr10 input differential reject peak voltage 5 mhz f 10 mhz 0 440 300 mv v icm10 input common mode voltage v cc /2 v v od10 output differential peak voltage rl = 100 w 2.2 2.8 v i cct10 line driver supply peak current rbias10 = 549 w 48 ma 1 figure 30. rbias10 resistance versus transmitter current rbias10 621.5 0hm 549 ohm 576 ohm icct10 19ma 20 ma 21ma
networking silicon 82559 datasheet 101 12.3 ac specifications notes: 1. switching current high specifications are not relevant to pme#, serr#, or inta#, which are open drain outputs. 2. maximum current requirements will be met as drivers pull beyond the first step voltage (ac drive point). equations defining these maximums (a and b) are provided. to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. this parameter is also applicable to cardbus environment. table 34. ac specifications for pci signaling symbol parameter condition min max units notes i oh(ac) switching current high 0 < v out 1.4 -44 ma 1 1.4 < v out < 0.9v cc -17.1(v cc - v out )ma1 0.7v cc < v out < v cc eqn a ma 2 (test point) v out = 0.7v cc -32v cc ma 2 i ol(ac) switching current low v out 3 2.2 95 ma 1 2.2 > v out > 0.1v cc v out /0.023 ma 1 0.18v cc > v out > 0 eqn b ma 2 (test point) v out = 0.18v cc 38v cc ma 2 i cl low clamp current -3 < v in -1 -25 + (v in + 1)/ 0.015 ma 3 i ch high clamp current v cc +4 > v in 3 v cc +1 25 + (v in -v cc -1)/ 0.015 ma 3 slew rp pci output rise slew rate 0.4 v to 2.4 v 1 4 v/ns slew fp pci output fall slew rate 2.4 v to 0.4 v 1 4 v/ns equation a. i oh = (98/v cc ) * (v out - v cc ) * (v out + 0.4v cc ), for v cc > v out > 0.7v cc equation b. i ol = (256/v cc ) * (v out ) * (v cc - v out ), for 0 < v out < 0.18v cc table 35. ac specifications for cardbus signaling symbol parameter condition min max units notes t rp cardbus output rise time 0.2v cc to 0.6v cc 0.25 1.0 v/ns t fp cardbus output fall time 0.6v cc to 0.2v cc 0.25 1.0 v/ns table 36. ac specifications for local bus signaling symbol parameter condition min max units notes i oh current output high 1 ma i ol current output low 2 ma
82559 networking silicon 102 datasheet 12.4 timing specifications 12.4.1 clocks specifications 12.4.1.1 pci/cardbus clock specifications the 82559 uses the pci clock signal directly. figure 31 shows the clock waveform and required measurement points for the pci clock signal. table 37 summarizes the pci clock specifications. notes: 1. the 82559 will work with any pci clock frequency up to 33 mhz. 2. rise and fall times are specified in terms of the edge rate measured in v/ns. this slew rate is met across the minimum peak-to-peak portion of the clock waveform as shown in figure 31 . 12.4.1.2 x1 specifications x1 serves as a signal input from an external crystal or oscillator. table 38 defines the 82559 requirements from this signal. figure 31. pci/cardbus clock waveform 0.6v cc 0.475v cc 0.4v cc 0.325v cc 0.2v cc 0.4v cc p -to- p ( minimum ) t_hi g h t_low t_c y c table 37. pci/cardbus clock specifications symbol parameter min max units notes t1 t cyc clk cycle time 30 ns 1 t2 t high clk high time 11 ns t3 t low clk low time 11 ns t4 t slew clk slew rate 1 4 v/ns 2 table 38. x1 clock specifications symbol parameter min typical max units notes t8 tx1_dc x1 duty cycle 40% 60% t9 tx1_pr x1 period 40 ns 50ppm
networking silicon 82559 datasheet 103 12.4.2 timing parameters 12.4.2.1 measurement and test conditions figure 32 , figure 33 , and table 39 define the conditions under which timing measurements are done. the component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. the design must guarantee that minimum timings are also met with maximum clock slew rate (fastest edge) and voltage swing. in addition, the design must guarantee proper input operation for input voltage swings and slew rates that exceed the specified test conditions. figure 32. output timing measurement conditions t_off t_on t_val v_ste p v_test v_test v_test v_th v_tl clk output delay tri-state output figure 33. input timing measurement conditions clk input v_test v_test v_test v_th v_tl v_th v_tl t_h t_su in p uts valid v_max table 39. measure and test condition parameters symbol pci level cardbus level units notes v th 0.6v cc 0.6v cc v v tl 0.2v cc 0.2v cc v
82559 networking silicon 104 datasheet note: input test is done with 0.1v cc overdrive. v max specifies the maximum peak-to-peak waveform allowed for testing input timing. 12.4.2.2 pci/cardbus timings notes: 1. timing measurement conditions are illustrated in figure 32 . 2. pci minimum times are specified with loads as detailed in the pci bus specification, revision 2.1, section 4.2.3.2. 3. cardbus minimum times are specified with a 0 pf equivalent load. maximum times are specified with a 30 pf equivalent load. actual test loads may vary but must be correlated to these loads. 4. n a pci environment, req# and gnt# are point-to-point signals and have different output valid delay times and input setup times than bussed signals. all other signals are bussed. 5. timing measurement conditions are illustrated in figure 33 . 6. rst# is asserted and de-asserted asynchronously with respect to the clk signal. 7. all pci and cardbus interface output drivers are floated when rst# is active. v test 0.4v cc 0.4v cc v v step (rising edge) 0.285v cc 0.325v cc v min delay 0.475v cc v max delay v step (falling edge) 0.615v cc 0.475v cc v min delay 0.325v cc v max delay v max 0.4v cc 0.4v cc v input signal edge rate 1 1 v/ns table 39. measure and test condition parameters table 40. pci/cardbus timing parameters symbol parameter min max units notes t14 t val pci clk to signal valid delay 2 11 ns 1, 2, 4 cardbus clk to signal valid delay 2 18 ns 1, 3 t15 t val(ptp) pci clk to signal valid delay (point- to-point) 2 12 ns 1, 2, 4 t16 t on float to active delay 2 ns 1 t17 t off active to float delay 28 ns 1 t18 t su input setup time to clk 7 ns 4, 5 t19 t su(ptp) pci input setup time to clk (point-to- point) 10 ns 4, 5 t20 t h input hold time from clk 0 ns 6 t21 t rst reset active time after power stable 1 ms 6 t22 t rst-clk pci reset active time after clk stable 100 m s6 cardbus reset active time after clk stable 100 clocks 6 t23 t rst-off reset active to output float delay 40 ns 6, 7
networking silicon 82559 datasheet 105 12.4.2.3 flash/modem interface timings the 82559 is designed to support up to 150 nanoseconds of flash access time. the v pp signal in the flash implementation should be connected permanently to 12 v. thus, writing to the flash is controlled only by the flwe# pin. table 41 provides the timing parameters for the flash interface signals. the timing parameters are illustrated in figure 34 and figure 35 . modem is supported through the flash interface when the following conditions apply: ? fla[6:0], fld[7:0], flcs#, floe#, and flwe# have the same functions for flash and modem. ? fla[8] acts as iochrdy asynchronous input in modem mode. table 41. flash timing parameters symbol parameter min max units notes t35 t flrwc flash read/write cycle time 150 ns 1, flash t avav = 150 ns t36 t flacc fla to read fld setup time 150 ns 1, flash t avqv = 150 ns t37 t flce flcs# to read fld setup time 150 ns 1, flash t elqv = 150 ns t38 t floe floe# active to read fld setup time 120 ns 1, flash t glqv = 55 ns t39 t fldf floe# inactive to fld driven delay time 50 ns 1, flash t ghqz = 35 ns t40 t flas fla setup time before flwe# 5 ns 2, flash t avwl = 0 ns t41 t flah fla hold time after flwe# 200 ns 2, flash t wlax = 60 ns t42 t flcs flcs# hold time before flwe# 30 ns 2, flash t elwl = 20 ns t43 t flch flcs# hold time after flwe# 30 ns 2, flash t wheh = 0 ns t44 t flds fld setup time 150 ns 2, flash t dvwh = 50 ns t45 t fldh fld hold time 10 ns 2, flash t whdx = 10 ns t46 t flwp write pulse width 120 ns 2, flash t wlwh = 60 ns t47 t flwph write pulse width high 25 ns 2, flash t whwl = 20 ns t48 t mioha iochrdy hold time after flwe# or floe# active 25 ns t49 t miohi iochrdy hold time after flwe# or floe# inactive 0ns
82559 networking silicon 106 datasheet notes: 1. these timing specifications apply to flash read cycles. the flash timings referenced are 28f020-150 timings. 2. these timing specifications apply to flash write cycles. the flash timings referenced are 28f020-150 timings. figure 34. flash/modem timings for a read cycle fladdr flcs# floe# fldata-r iochrdy address stable data in t35 t37 t38 t39 t48 t49 t36 figure 35. flash/modem timings for a write cycle fladdr flcs# flwe# fldata-w iochrdy address stable data out t35 t40 t41 t42 t46 t43 t47 t44 t45 t48 t49
networking silicon 82559 datasheet 107 12.4.2.4 eeprom interface timings the 82559 is designed to support a standard 64x16 or 256x16 serial eeprom. table 42 provides the timing parameters for the eeprom interface signals. the timing parameters are illustrated in figure 36 . table 42. eeprom timing parameters symbol parameter min max units notes t50 t efsk serial clock frequency 1 mhz eeprom fsk = 1 mhz t51 t ecss delay from eecs high to eesk high 300 ns eeprom tcss = 50 ns t52 t ecsh delay from eesk low to eecs low 30 ns eeprom tcsh = 0 ns t53 t edis setup time of eedi to eesk 300 ns eeprom tdis = 150 ns t54 t edih hold time of eedi after eesk 300 ns eeprom tdih = 150 ms t55 t ecs eecs low time 750 ns eeprom tcs = 250 ns figure 36. eeprom timings eecs fla15eesk fla13eedi t51 t52 t54 t53
82559 networking silicon 108 datasheet 12.4.2.5 phy timings table 43. 10base-t nlp timing parameters symbol parameter condition min typ max units t56 t nlp_wid nlp width 10 mbps 100 ns t57 t nlp_per nlp period 10 mbps 8 24 ms figure 37. 10base-t nlp timings normal link pulse t57 t56 table 44. auto-negotiation flp timing parameters symbol parameter min typ max units t58 t flp_wid flp width (clock/data) 100 ns t59 t flp_clk_clk clock pulse to clock pulse period 111 125 139 m s t60 t flp_clk_dat clock pulse to data pulse period 55.5 62.5 69.5 m s t61 t flp_bur_num number of pulses in one burst 17 33 t62 t flp_bur_wid flp burst width 2 ms t63 t flp_bur_per flp burst period 8 24 ms figure 38. auto-negotiation flp timings fast link pulse t60 t58 t59 clock pulse data pulse clock pulse flp bursts t62 t63
networking silicon 82559 datasheet 109 12.4.2.6 smb interface timings table 45. 100base-tx transmitter ac specification symbol parameter condition min typ max units t64 t jit tdp/tdn differential output peak jitter hls data 1400 ps table 46. flash timing parameters symbol parameter min max units notes f smb smb operating frequency 1 mhz t84 t dhs data hold time 300 ns t85 t dsus data setup time 250 ns
82559 networking silicon 110 datasheet
networking silicon 82559 datasheet 111 13.0 package and pinout information 13.1 package information the 82559 is a 196-pin ball grid array (bga) package. package dimensions are shown in figure 39 . more information on intel device packaging is available in the intel packaging handbook, which is available from the intel literature center or your local intel sales office. figure 39. dimension diagram for the 82559 196-pin bga
82559 networking silicon 112 datasheet 13.2 pinout information 13.2.1 82559 pin assignments table 47. 82559 pin assignments pin name pin name pin name a1 nc a2 serr# a3 vcc a4 idsel a5 ad25 a6 pme# a7 vcc a8 ad30 a9 altrst# a10 smbclk a11 vcc a12 liled a13 test a14 nc b1 ad22 b2 ad23 b3 vsspp b4 ad24 b5 ad26 b6 ad27 b7 vsspp b8 ad31 b9 isolate# b10 smbalrt# b11 speedled b12 to b13 rbias100 b14 rbias10 c1 ad21 c2 rst# c3 req# c4 c/be3# c5 cstschg c6 ad28 c7 ad29 c8 clkrun# c9 smbd c10 vsspt c11 actled c12 vref c13 tdp c14 tdn d1 ad18 d2 ad19 d3 ad20 d4 vss d5 vss d6 vss d7 vss d8 vss d9 nc d10 nc d11 vss d12 ti d13 texec d14 tck e1 vcc e2 vsspp e3 ad17 e4 vss e5 vss e6 vss e7 vss e8 vss e9 vss e10 vss e11 vss e12 vcc e13 rdp e14 rdn f1 irdy# f2 frame# f3 c/be2# f4 vss f5 vss f6 vss f7 vss f8 vss f9 vss f10 vss f11 vss f12 fld2 f13 fld1 f14 fld0 g1 clk g2 vio g3 trdy# g4 nc g5 vcc g6 vcc g7 vss g8 vss g9 vss g10 vss g11 vss g12 fld3
networking silicon 82559 datasheet 113 g13 vcc g14 vsspl h1 stop# h2 inta# h3 devsel# h4 nc h5 vcc h6 vcc h7 vcc h8 vcc h9 vss h10 vss h11 vss h12 fld6 h13 fld5 h14 fld4 j1 par j2 perr# j3 gnt# j4 nc j5 vcc j6 vcc j7vccj8vccj9vcc j10 vcc j11 vcc j12 fla1 j13 fla0 j14 fld7 k1 ad16 k2 vsspp k3 vcc k4 vcc k5 vcc k6 vcc k7 vcc k8 vcc k9 vcc k10 vcc k11 vcc k12 vsspl k13 vcc k14 fla2 l1 ad14 l2 ad15 l3 c/be#1 l4 vcc l5 vcc l6 vss l7 cfcs# l8 cfclk l9 vcc l10 vcc l11 vss l12 fla5 l13 fla4 l14 fla3 m1 ad11 m2 ad12 m3 ad13 m4 c/be0# m5 ad5 m6 vsspp m7 ad1 m8 floe# m9 flwe# m10 fla15/eesk m11 fla12 m12 fla11 m13fla7m14fla6 n1 vsspp n2 ad10 n3 ad9 n4 ad7 n5 ad4 n6 vcc n7 ad0 n8 vcc n9 flcs# n10 fla14/eedo n11 x1 n12 vsspl n13 fla10 n14 fla8/iochrdy p1 nc p2 vcc p3 ad8 p4 ad6 p5 ad3 p6 ad2 p7 eecs p8 vsspl p9 fla16 p10 fla13/eedi p11 x2 p12 vcc p13 fla9 p14 nc table 47. 82559 pin assignments pin name pin name pin name
82559 networking silicon 114 datasheet 13.2.2 82559 ball grid array diagram figure 40. 82559 ball grid array diagram nc fla9 vccpl x2 fla13/ eedi fla16 vsspl eecs ad2 ad3 ad6 ad8 vccpp nc fla8 fla10 vsspl x1 fla14/ eedo flcs# vccpl ad0 vccpp ad4 ad7 ad9 ad10 vsspp fla6 fla7 fla11 fla12 fla15/ eesk flwe# floe# ad1 vsspp ad5 cbe0# ad13 ad12 ad11 fla3 fla4 fla5 vss vcc vcc cfclk cfcs vss vcc vcc cbe1# ad15 ad14 fla2 vccpl vsspl vcc vcc vcc vcc vcc vcc vcc vcc vccpp vsspp ad16 fld7 fla0 fla1 vcc vcc vcc vcc vcc vcc vcc nc gnt# perr# par fld4 fld5 fld6 vss vss vss vcc vcc vcc vcc nc devsel # inta# stop# vsspl vccpl fld3 vss vss vss vss vss vcc vcc nc trdy# vio clk fld0 fld1 fld2 vss vss vss vss vss vss vss vss cbe2# frame# irdy# rdn rdp vcc vss vss vss vss vss vss vss vss ad17 vsspp vccpp tck texec ti vss nc nc vss vss vss vss vss ad20 ad19 ad18 tdn tdp vref actled vsspt smbd clkru n# ad29 ad28 cstsc hg cbe3# req# rst# ad21 rbias1 0 rbias1 00 to speedl ed smbal rt# isolat e# ad31 vsspp ad27 ad26 ad24 vsspp ad23 ad22 nc test liled vccpt smbcl k altrst # ad30 vccpp pme# ad25 idsel vccpp serr# nc a b c d e f g h j k l m n p 1 2 3 4 5 6 7 8 9 10 11 12 13 14 82559 ballout bga196 15mmx15mm ( top view ) 4 ma y 98

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